DIPLOMARBEIT - FG Mikroelektronik, TU Berlin
DIPLOMARBEIT - FG Mikroelektronik, TU Berlin
DIPLOMARBEIT - FG Mikroelektronik, TU Berlin
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Abbildung 55: Speedchart-Diagramm VIDEO/VRAM/VR RAM/READ WRITE<br />
READ_WRITE<br />
Subdiag Actions of <br />
A: A_RAMr_ot:=0x0;<br />
C: CAS_falling=’1’<br />
A: print "PageMode_Mask_BW"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv(8 downto 2)<br />
& " ColSel=" & DIN_itv<br />
& " Data(Col)=" & Color;<br />
A_RAMw_ot:=0x3;<br />
A_ROW_ot:=Row;<br />
A_COL_ot(8 downto 2):=RCA_itv(8 downto 2);<br />
A_COL_ot(1 downto 0):="00";<br />
A_RCSL_ot:=DIN_itv;<br />
A: A_RAMw_ot:=0x0;<br />
T31 #1<br />
T1 #2<br />
T32 #1<br />
Mask_BW<br />
T2 #2<br />
A: A_RAMw_ot:=0x0;<br />
Mask_FW<br />
C: CAS_falling=’1’<br />
A: print "PageMode_BW"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv(8 downto 2)<br />
& " Data(Col)=" & Color;<br />
A_RAMw_ot:=0x5;<br />
A_ROW_ot:=Row;<br />
A_COL_ot(8 downto 2):=RCA_itv(8 downto 2);<br />
A_COL_ot(1 downto 0):="00";<br />
A_DATA_ot:=Color;<br />
BW<br />
C: RAS_WE=’0’ and RAS_SF=’0’ and MSF_itv=’1’<br />
A: print "Mask_BW"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv(8 downto 2)<br />
& " ColSel=" & DIN_itv<br />
& " Data(Col)=" & Color;<br />
A_RAMw_ot:=0x2;<br />
A_ROW_ot:=Row;<br />
A_COL_ot(8 downto 2):=RCA_itv(8 downto 2);<br />
A_COL_ot(1 downto 0):="00";<br />
A_RCSL_ot:=DIN_itv;<br />
A_DATA_ot:=Color;<br />
C: RAS_WE=’0’ and RAS_SF=’1’<br />
A: print "Mask_FW"<br />
& " Row=" & Row<br />
& " Mask=" & WM1<br />
& " Data(Col)=" & Color;<br />
A_RAMw_ot:=0x1;<br />
A_ROW_ot:=Row;<br />
A_WM1_ot:=WM1;<br />
A_DATA_ot:=Color;<br />
T15<br />
T14<br />
T17<br />
C: RAS_WE=’1’ and RAS_SF=’0’ and MSF_itv=’1’<br />
A: print "BW"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv(8 downto 2)<br />
& " Data(Col)=" & Color;<br />
A_RAMw_ot:=0x4;<br />
A_ROW_ot:=Row;<br />
A_COL_ot(8 downto 2):=RCA_itv(8 downto 2);<br />
A_COL_ot(1 downto 0):="00";<br />
A_DATA_ot:=Color;<br />
C: RAS_WE=’0’ and RAS_SF=’0’ and MSF_itv=’0’<br />
A: if MWE_itv=’0’ then<br />
print "Mask_W(early)"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv<br />
& " Mask=" & WM1<br />
& " Data=" & DIN_itv;<br />
A_RAMw_ot:=0xC;<br />
A_ROW_ot:=Row;<br />
A_COL_ot:=RCA_itv(8 downto 0);<br />
A_WM1_ot:=WM1;<br />
A_DATA_ot:=DIN_itv;<br />
end if;<br />
Column:=RCA_itv(8 downto 0);<br />
entry<br />
T18<br />
T13<br />
C: RAS_WE=’1’ and RAS_SF=’0’<br />
and MSF_itv=’0’<br />
A: if MWE_itv=’0’ then<br />
print "Write(early)"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv<br />
& " Data=" & DIN_itv;<br />
A_RAMw_ot:=0x8;<br />
A_ROW_ot:=Row;<br />
A_COL_ot:=RCA_itv(8 downto 0);<br />
A_DATA_ot:=DIN_itv;<br />
end if;<br />
Column:=RCA_itv(8 downto 0);<br />
T16<br />
C: RAS_WE=’1’ and RAS_SF=’1’<br />
A: if MWE_itv=’0’ then<br />
Color:=DIN_itv;<br />
flag:=’1’;<br />
print "Load_Col(early)"<br />
& " C=" & DIN_itv;<br />
A_RAMw_ot:=0x6;<br />
A_DATA_ot:=DIN_itv;<br />
else<br />
flag:=’0’;<br />
end if;<br />
T25<br />
Color<br />
State_action of <br />
A: if MOE_itv=’0’ then<br />
D_out(24 downto 16):=Row;<br />
D_out( 8 downto 0):=Column;<br />
D_oe:=’1’;<br />
print "RMW_perBit_Read"<br />
& " Row=" & Row<br />
& " Col=" & Column;<br />
A_RAMr_ot:=0x2;<br />
A_RROW_ot:=Row;<br />
A_RCOL_ot:=Column;<br />
end if;<br />
A: A_RAMw_ot:=0x0;<br />
T3 #4<br />
Mask_W<br />
T35 #3<br />
T34 #2<br />
T33 #1<br />
C: CAS_falling=’1’<br />
-- and MWE_itv=’1’<br />
A: Column:=RCA_itv(8 downto 0);<br />
print "PageMode_Link";<br />
A_RAMw_ot:=0x9;<br />
State_action of <br />
A: if MOE_itv=’0’ then<br />
D_out(24 downto 16):=Row;<br />
D_out( 8 downto 0):=Column;<br />
D_oe:=’1’;<br />
print "Read"<br />
& " Row=" & Row<br />
& " Col=" & Column;<br />
A_RAMr_ot:=0x1;<br />
A_RROW_ot:=Row;<br />
A_RCOL_ot:=Column;<br />
end if;<br />
RW<br />
T38 #2<br />
C: CAS_falling=’1’ and MWE_itv=’0’<br />
A: print "PageMode_Mask_W(early)"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv<br />
& " Mask=" & WM1<br />
& " Data=" & DIN_itv;<br />
A_RAMw_ot:=0xE;<br />
A_ROW_ot:=Row;<br />
A_COL_ot:=RCA_itv(8 downto 0);<br />
A_WM1_ot:=WM1;<br />
A_DATA_ot:=DIN_itv;<br />
C: MWE_falling=’1’<br />
A: print "Mask_W(WE_ctr)"<br />
& " Row=" & Row<br />
& " Col=" & Column<br />
& " Mask=" & WM1<br />
& " Data=" & DIN_itv;<br />
A_RAMw_ot:=0xD;<br />
A_ROW_ot:=Row;<br />
A_COL_ot:=Column;<br />
A_WM1_ot:=WM1;<br />
A_DATA_ot:=DIN_itv;<br />
C: CAS_falling=’1’ and MWE_itv=’0’<br />
A: print "PageMode_Write(early)"<br />
& " Row=" & Row<br />
& " Col=" & RCA_itv<br />
& " Data=" & DIN_itv;<br />
A_RAMw_ot:=0xB;<br />
A_ROW_ot:=Row;<br />
A_COL_ot:=RCA_itv(8 downto 0);<br />
A_DATA_ot:=DIN_itv;<br />
A: A_RAMw_ot:=0x0;<br />
T4 #4<br />
C: MWE_falling=’1’<br />
A: print "Write(WE_ctr)"<br />
T39 #1<br />
& " Row=" & Row<br />
& " Col=" & Column<br />
T40 #3<br />
& " Data=" & DIN_itv;<br />
C: CAS_falling=’1’<br />
A_RAMw_ot:=0xA;<br />
-- and MWE_itv=’1’<br />
A_ROW_ot:=Row;<br />
A: Column:=RCA_itv(8 downto 0);<br />
A_COL_ot:=Column;<br />
print "PageMode_Link";<br />
A_RAMw_ot:=0x9;<br />
A_DATA_ot:=DIN_itv;<br />
C: MWE_falling=’1’ and MOE_itv=’1’<br />
A: Color:=DIN_itv;<br />
flag:=’1’;<br />
print "Load_Col(delayed) C=" & DIN_itv;<br />
A_RAMw_ot:=0x7;<br />
A_DATA_ot:=DIN_itv;<br />
State_action of <br />
A: if flag=’0’ and MOE_itv=’0’then<br />
D_out:=Color;<br />
D_oe:=’1’;<br />
print "Read_Col C=" & Color;<br />
A_RAMr_ot:=0x3;<br />
end if;<br />
Technische Universität <strong>Berlin</strong><br />
Institut für <strong>Mikroelektronik</strong><br />
Lukas Bauer<br />
Diplomarbeit<br />
Hochleistungs-Grafikprozessor in Speedchart-VHDL<br />
Anhang C.2<br />
Seite 88
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