DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Abbildung 92: Speedchart-Diagramm TIM/CONTROL/TIM ACCESS/REG WRITE
REG_WRITE
entry
T1 T2 T3 T4 T5
S1
S2
S3
S4
A: -- write upper byte of register
A: -- write higher byte of register
A: -- write middle byte of register
A: -- write lower byte of register
if BS_lat(3)=’0’ then
if BS_lat(2)=’0’ then
if BS_lat(1)=’0’ then
if BS_lat(0)=’0’ then
case ADS_lat is
case ADS_lat is
case ADS_lat is
case ADS_lat is
-- when 0 => null; -- R_STATUS is read only
when 1 => if LOCK=’0’ then
when 0 => R_IMASK := DATA_IN(23 downto 16);
when 0 => R_LINTV (15 downto 08) := DATA_IN(15 downto 8);
when 0 => R_LINTV (07 downto 00) := DATA_IN(7 downto 0);
R_CONFIG (31 downto 24) := DATA_IN(31 downto 24);
when 1 => if LOCK=’0’ then
when 1 => if LOCK=’0’ then
when 1 => if LOCK=’0’ then
end if;
R_CONFIG (23 downto 16) := DATA_IN(23 downto 16);
R_CONFIG (15 downto 08) := DATA_IN(15 downto 8);
R_CONFIG (07 downto 00) := DATA_IN(7 downto 0);
when 2 => if LOCK=’0’ then
end if;
elsif (DATA_IN(15 downto 8)=0x7F) then
end if;
R_MUXOFF (15 downto 08) := DATA_IN(31 downto 24);
when 2 => if LOCK=’0’ then
unlock:=’1’; -- ready for 7F-unlock
end if;
R_MUXOFF (07 downto 00) := DATA_IN(23 downto 16);
elsif (DATA_IN(15 downto 8)=0x55 and unlock=’1’) then when 2 => R_XYZOOM := DATA_IN(7 downto 0);
end if;
R_CONFIG (15):=’0’; -- 55 after 7F clears LOCK !
when 3 => R_DINC (07 downto 00) := DATA_IN(7 downto 0);
when 3 => R_SINC (15 downto 08) := DATA_IN(31 downto 24);
unlock:=’0’;
when 4 => R_4 (07 downto 00) := DATA_IN(7 downto 0);
when 4 => R_4 (31 downto 24) := DATA_IN(31 downto 24);
when 3 => R_SINC (07 downto 00) := DATA_IN(23 downto 16);
else
when 5 => R_5 (07 downto 00) := DATA_IN(7 downto 0);
when 5 => R_5 (31 downto 24) := DATA_IN(31 downto 24);
when 4 => R_4 (23 downto 16) := DATA_IN(23 downto 16);
unlock:=’0’; -- other value, 7F will not unlock.
when 6 => R_SSTART (07 downto 00) := DATA_IN(7 downto 0);
when 6 => R_SSTART (31 downto 24) := DATA_IN(31 downto 24);
when 5 => R_5 (23 downto 16) := DATA_IN(23 downto 16);
end if;
when 7 => R_DSTART (07 downto 00) := DATA_IN(7 downto 0);
when 7 => R_DSTART (31 downto 24) := DATA_IN(31 downto 24);
when 6 => R_SSTART (23 downto 16) := DATA_IN(23 downto 16);
when 2 => if LOCK=’0’ then
when 8 => R_DPYSTRT (07 downto 00) := DATA_IN(7 downto 0);
when 8 => R_DPYSTRT (31 downto 24) := DATA_IN(31 downto 24);
when 7 => R_DSTART (23 downto 16) := DATA_IN(23 downto 16);
R_RADSEL := DATA_IN(15 downto 8);
when 9 => R_DPYNXT (07 downto 00) := DATA_IN(7 downto 0);
when 9 => R_DPYNXT (31 downto 24) := DATA_IN(31 downto 24);
when 8 => R_DPYSTRT (23 downto 16) := DATA_IN(23 downto 16);
end if;
when 10 => R_DPYMASK (07 downto 00) := DATA_IN(7 downto 0);
when 10 => R_DPYINC (15 downto 08) := DATA_IN(31 downto 24);
when 9 => R_DPYNXT (23 downto 16) := DATA_IN(23 downto 16);
when 11 => R_SADR (07 downto 00) := DATA_IN(7 downto 0);
when 11 => R_SADR (31 downto 24) := DATA_IN(31 downto 24);
when 10 => R_DPYINC (07 downto 00) := DATA_IN(23 downto 16);
when 3 => R_DINC (15 downto 08) := DATA_IN(15 downto 8);
when 12 => R_DADR (07 downto 00) := DATA_IN(7 downto 0);
when 12 => R_DADR (31 downto 24) := DATA_IN(31 downto 24);
when 11 => R_SADR (23 downto 16) := DATA_IN(23 downto 16);
when 4 => R_4 (15 downto 08) := DATA_IN(15 downto 8);
when 13 => R_DY (07 downto 00) := DATA_IN(7 downto 0);
when 13 => R_DX (15 downto 08) := DATA_IN(31 downto 24);
when 12 => R_DADR (23 downto 16) := DATA_IN(23 downto 16);
when 5 => R_5 (15 downto 08) := DATA_IN(15 downto 8);
when 14 => R_14 (07 downto 00) := DATA_IN(7 downto 0);
when 14 => R_PSIZE := DATA_IN(31 downto 24);
when 13 => R_DX (07 downto 00) := DATA_IN(23 downto 16);
when 6 => R_SSTART (15 downto 08) := DATA_IN(15 downto 8);
when 15 => R_COMMAND := DATA_IN(7 downto 0);
when 15 => R_AUXREG := DATA_IN(31 downto 24);
when 14 => R_PATTNSIZE := DATA_IN(23 downto 16);
when 7 => R_DSTART (15 downto 08) := DATA_IN(15 downto 8);
when 16 => R_COLOR0 (07 downto 00) := DATA_IN(7 downto 0);
when 16 => R_COLOR0 (31 downto 24) := DATA_IN(31 downto 24);
when 15 => R_HDREG := DATA_IN(23 downto 16);
when 8 => R_DPYSTRT (15 downto 08) := DATA_IN(15 downto 8);
when 17 => R_COLOR1 (07 downto 00) := DATA_IN(7 downto 0);
when 17 => R_COLOR1 (31 downto 24) := DATA_IN(31 downto 24);
when 16 => R_COLOR0 (23 downto 16) := DATA_IN(23 downto 16);
when 9 => R_DPYNXT (15 downto 08) := DATA_IN(15 downto 8);
when 18 => R_COLOR2 (07 downto 00) := DATA_IN(7 downto 0);
when 18 => R_COLOR2 (31 downto 24) := DATA_IN(31 downto 24);
when 17 => R_COLOR1 (23 downto 16) := DATA_IN(23 downto 16);
when 10 => R_DPYMASK (15 downto 08) := DATA_IN(15 downto 8);
when 19 => R_COLOR3 (07 downto 00) := DATA_IN(7 downto 0);
when 19 => R_COLOR3 (31 downto 24) := DATA_IN(31 downto 24);
when 18 => R_COLOR2 (23 downto 16) := DATA_IN(23 downto 16);
when 11 => R_SADR (15 downto 08) := DATA_IN(15 downto 8);
when 20 => R_WENDX (07 downto 00) := DATA_IN(7 downto 0);
when 20 => R_WSTARTX (15 downto 08) := DATA_IN(31 downto 24);
when 19 => R_COLOR3 (23 downto 16) := DATA_IN(23 downto 16);
when 12 => R_DADR (15 downto 08) := DATA_IN(15 downto 8);
when 21 => R_WENDY (07 downto 00) := DATA_IN(7 downto 0);
when 21 => R_WSTARTY (15 downto 08) := DATA_IN(31 downto 24);
when 20 => R_WSTARTX (07 downto 00) := DATA_IN(23 downto 16);
when 13 => R_DY (15 downto 08) := DATA_IN(15 downto 8);
when 22 => R_SETVCNT (07 downto 00) := DATA_IN(7 downto 0);
when 22 => R_SETHCNT (15 downto 08) := DATA_IN(31 downto 24);
when 21 => R_WSTARTY (07 downto 00) := DATA_IN(23 downto 16);
when 14 => R_14 (15 downto 08) := DATA_IN(15 downto 8);
when 23 => R_23 (07 downto 00) := DATA_IN(7 downto 0);
when 23 => R_23 (31 downto 24) := DATA_IN(31 downto 24);
when 22 => R_SETHCNT (07 downto 00) := DATA_IN(23 downto 16);
when 15 => R_COMCTRL := DATA_IN(15 downto 8);
when 24 => R_HESYNC (07 downto 00) := DATA_IN(7 downto 0);
when 24 => R_HCOUNT (15 downto 08) := DATA_IN(31 downto 24);
when 23 => R_23 (23 downto 16) := DATA_IN(23 downto 16);
when 16 => R_COLOR0 (15 downto 08) := DATA_IN(15 downto 8);
when 25 => R_HSBLNK (07 downto 00) := DATA_IN(7 downto 0);
when 25 => R_HEBLNK (15 downto 08) := DATA_IN(31 downto 24);
when 24 => R_HCOUNT (07 downto 00) := DATA_IN(23 downto 16);
when 17 => R_COLOR1 (15 downto 08) := DATA_IN(15 downto 8);
when 26 => R_HESERR (07 downto 00) := DATA_IN(7 downto 0);
when 26 => R_HTOTAL (15 downto 08) := DATA_IN(31 downto 24);
when 25 => R_HEBLNK (07 downto 00) := DATA_IN(23 downto 16);
when 18 => R_COLOR2 (15 downto 08) := DATA_IN(15 downto 8);
when 27 => R_VESYNC (07 downto 00) := DATA_IN(7 downto 0);
when 27 => R_VCOUNT (15 downto 08) := DATA_IN(31 downto 24);
when 26 => R_HTOTAL (07 downto 00) := DATA_IN(23 downto 16);
when 19 => R_COLOR3 (15 downto 08) := DATA_IN(15 downto 8);
when 28 => R_VSBLNK (07 downto 00) := DATA_IN(7 downto 0);
when 28 => R_VEBLNK (15 downto 08) := DATA_IN(31 downto 24);
when 27 => R_VCOUNT (07 downto 00) := DATA_IN(23 downto 16);
when 20 => R_WENDX (15 downto 08) := DATA_IN(15 downto 8);
when 29 => R_29 (07 downto 00) := DATA_IN(7 downto 0);
when 29 => R_VTOTAL (15 downto 08) := DATA_IN(31 downto 24);
when 28 => R_VEBLNK (07 downto 00) := DATA_IN(23 downto 16);
when 21 => R_WENDY (15 downto 08) := DATA_IN(15 downto 8);
when 30 => R_30 (07 downto 00) := DATA_IN(7 downto 0);
when 30 => R_30 (31 downto 24) := DATA_IN(31 downto 24);
when 29 => R_VTOTAL (07 downto 00) := DATA_IN(23 downto 16);
when 22 => R_SETVCNT (15 downto 08) := DATA_IN(15 downto 8);
when 31 => R_31 (07 downto 00) := DATA_IN(7 downto 0);
when 31 => R_31 (31 downto 24) := DATA_IN(31 downto 24);
when 30 => R_30 (23 downto 16) := DATA_IN(23 downto 16);
when 23 => R_23 (15 downto 08) := DATA_IN(15 downto 8);
when 32 => R_PATTN003 := DATA_IN(7 downto 0);
when 32 => R_PATTN000 := DATA_IN(31 downto 24);
when 31 => R_31 (23 downto 16) := DATA_IN(23 downto 16);
when 24 => R_HESYNC (15 downto 08) := DATA_IN(15 downto 8);
when 33 => R_PATTN007 := DATA_IN(7 downto 0);
when 33 => R_PATTN004 := DATA_IN(31 downto 24);
when 32 => R_PATTN001 := DATA_IN(23 downto 16);
when 25 => R_HSBLNK (15 downto 08) := DATA_IN(15 downto 8);
-- etc...
-- etc...
when 33 => R_PATTN005 := DATA_IN(23 downto 16);
when 26 => R_HESERR (15 downto 08) := DATA_IN(15 downto 8);
end case;
end case;
-- etc...
when 27 => R_VESYNC (15 downto 08) := DATA_IN(15 downto 8);
print "write R L#" & ADS_lat & " data " & DATA_IN(7 downto 0);
print "write R U#" & ADS_lat & " data " & DATA_IN(31 downto 24); end case;
when 28 => R_VSBLNK (15 downto 08) := DATA_IN(15 downto 8); end if;
end if;
print "write R H#" & ADS_lat & " data " & DATA_IN(23 downto 16);
when 29 => R_29 (15 downto 08) := DATA_IN(15 downto 8);
end if;
when 30 => R_30 (15 downto 08) := DATA_IN(15 downto 8);
when 31 => R_31 (15 downto 08) := DATA_IN(15 downto 8);
when 32 => R_PATTN002 := DATA_IN(15 downto 8);
when 33 => R_PATTN006 := DATA_IN(15 downto 8);
-- etc...
end case;
print "write R M#" & ADS_lat & " data " & DATA_IN(15 downto 8);
end if;
exit
Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang D.2
Seite 122