DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
MEM_ADDRESS
Subdiag Actions of
V: CAS_M(4): logic:=lo4; -- CAS mask
--
A: RAM_ADDR:=lo32; -- no memory access
CAS_MASK:=hi4; -------------------
RAM_D_W:=lo32;
ANY_CYCLE:=’0’;
MEM_GREAD:=’0’;
MEM_GWRITE:=’0’;
if MEM_READ=’1’ then -- host data read
-----------------
ANY_CYCLE:=bnot READ_DONE; -- perform memory access
RAM_ADDR:=A_READ; -- read address
CAS_M:=CAS_READ; -- CAS mask
elsif FIFO_IN/=FIFO_OUT then -- host data write
------------------
ANY_CYCLE:=’1’; -- perform memory access
case (FIFO_OUT mod 4) is -- get from write fifo:
when 0 =>
RAM_ADDR:=A_FIFO0; -- write address
RAM_D_W :=D_FIFO0; -- write data
CAS_M:=CAS_FIFO0; -- CAS mask
when 1 =>
RAM_ADDR:=A_FIFO1;
RAM_D_W :=D_FIFO1;
CAS_M:=CAS_FIFO1;
when 2 =>
RAM_ADDR:=A_FIFO2;
RAM_D_W :=D_FIFO2;
CAS_M:=CAS_FIFO2;
when 3 =>
RAM_ADDR:=A_FIFO3;
RAM_D_W :=D_FIFO3;
CAS_M:=CAS_FIFO3;
end case;
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
elsif GPU_READ=’1’ or GREAD_END=’1’ then -- gr-command data read
----------------------if
GPU_READ=’1’ then
ANY_CYCLE:=’1’; -- perform memory access
end if;
MEM_GREAD:=’1’;
RAM_ADDR:=SADRLW_C shl 2; -- current read address (LW->byte)
if SADRLW_C=SADRLW_L then
if SADRLW_C/=SADRLW_R then -- leftmost longword ?
CAS_M:=SCMASK_L; -- only read relevant bytes (l)
else -- one longword only ?
CAS_M:=SCMASK_L bor SCMASK_R; -- only read relevant bytes (m)
end if;
elsif SADRLW_C=SADRLW_R then -- rightmost longword ?
CAS_M:=SCMASK_R; -- only read relevant bytes (r)
else -- in between
CAS_M:="0000"; -- read all 4 bytes
end if;
elsif GPU_WRITE=’1’ then -- gr-command data write
------------------------
ANY_CYCLE:=’1’; -- perform memory access
MEM_GWRITE:=’1’;
RAM_ADDR:=DADRLW_C shl 2; -- current write address (LW->byte)
if DADRLW_C=DADRLW_L then
if DADRLW_C/=DADRLW_R then -- leftmost longword ?
CAS_M:=DCMASK_L; -- only write relev. bytes (l)
PRE_MASK:=DBMASK_L; -- use left-hand side bit mask
PRE_READ:=’1’ -- read dest. before writing
when ((DBOS_L mod 8)/=0 -- if dest. isn’t byte-aligned
or S(1 downto 0)/="00") -- or source and dest. are comb.
else ’0’;
else -- one longword only ?
CAS_M:=DCMASK_L bor DCMASK_R; -- only write relev. bytes (m)
PRE_MASK:=DBMASK_L band DBMASK_R; -- "and" bit masks
PRE_READ:=’1’ -- read dest. before writing
when ((DBOS_L mod 8)/=0 -- if source or destination
or (DBOS_R mod 8)/=7 -- isn’t byte-aligned
or S(1 downto 0)/="00") -- or source and dest. are comb.
else ’0’;
end if;
elsif DADRLW_C=DADRLW_R then -- rightmost longword ?
CAS_M:=DCMASK_R; -- only write relev. bytes (r)
PRE_MASK:=DBMASK_R; -- use right-hand side bit mask
PRE_READ:=’1’ -- read dest. before writing
when ((DBOS_R mod 8)/=7 -- if dest. isn’t byte-aligned
or S(1 downto 0)/="00") -- or source and dest. are comb.
else ’0’;
else -- in between
CAS_M:="0000"; -- write all 4 bytes
PRE_READ:=’1’ -- only read destination
when S(1 downto 0)/="00" -- if source and dest. are comb.
else ’0’;
PRE_MASK:=hi32; -- all GPU FIFO data bits valid
end if;
case GPU_FIFO_OUT is -- get data from GPU fifo buffer
when 0 => D_GPU_FIFO:=D_GPU_FIFO0;
when 1 => D_GPU_FIFO:=D_GPU_FIFO1;
when 2 => D_GPU_FIFO:=D_GPU_FIFO2;
when 3 => D_GPU_FIFO:=D_GPU_FIFO3;
when 4 => D_GPU_FIFO:=D_GPU_FIFO4;
when 5 => D_GPU_FIFO:=D_GPU_FIFO5;
when 6 => D_GPU_FIFO:=D_GPU_FIFO6;
when 7 => D_GPU_FIFO:=D_GPU_FIFO7;
when 8 => D_GPU_FIFO:=D_GPU_FIFO8;
end case;
RAM_D_W:=WRITE_DATA; -- from diagram PIXBLT_PATH
end if;
CAS_MASK:=CAS_M bor CAS_DONE; -- don’t read the same bytes again
Abbildung 98: Speedchart-Diagramm TIM/CONTROL/MEM ACCESS/MEM ADDRESS
Anhang D.2
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