DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Abbildung 94: Speedchart-Diagramm TIM/CONTROL/MEM ACCESS/MEM CYCLES
MEM_CYCLES
Entry of
A: -- MWE_ict:=’0’ when write access
-- D_ict :=(write data) & (activate D_oe when write)
-- RCA_ict:=(CAS address)
-- CAS_lat:=(CAS mask) (not applied to RAM port yet)
-- mark written bytes in CAS_DONE
if MEM_READ=’1’ or MEM_GREAD=’1’ then
MOE_ict:=’0’; -- memory read
MWE_ict:=’1’;
elsif MEM_GWRITE=’1’ and PRE_READ=’1’ then
MEM_RMW:=’1’; -- memory read-modify-write cycle
MOE_ict:=’0’;
MWE_ict:=’1’;
else
MWE_ict:=’0’; -- memory write
DOE_ict:=hi32; -- data lines as outputs
end if;
case MBW is
when "00" =>
CAS_lat:="1110";
RCA_ict(13 downto 2):=RAM_COL(13 downto 2);
if CAS_MASK(3)=’0’ then
RCA_ict(1 downto 0):="00"; -- byte U
CAS_DONE(3):=’1’; -- done
D_ict(7 downto 0):=RAM_D_W(31 downto 24);
end if;
if CAS_MASK(3 downto 2)="10" then
RCA_ict(1 downto 0):="01"; -- byte H
CAS_DONE(2):=’1’; -- done
D_ict(7 downto 0):=RAM_D_W(23 downto 16);
end if;
if CAS_MASK(3 downto 1)="110" then
RCA_ict(1 downto 0):="10"; -- byte M
CAS_DONE(1):=’1’; -- done
D_ict(7 downto 0):=RAM_D_W(15 downto 08);
end if;
if CAS_MASK="1110" then
RCA_ict(1 downto 0):="11"; -- byte L
CAS_DONE(0):=’1’; -- done
D_ict(7 downto 0):=RAM_D_W(07 downto 00);
end if;
when "01" =>
RCA_ict(13 downto 1):=RAM_COL(13 downto 1);
CAS_lat(3 downto 2):="11";
if CAS_MASK(3 downto 2)/="11" then
CAS_lat(1 downto 0):=CAS_MASK(3 downto 2);
RCA_ict(0):=’0’; -- byte U+H
CAS_DONE(3 downto 2):="11"; -- done
D_ict(15 downto 00):=RAM_D_W(31 downto 16);
else
CAS_lat(1 downto 0):=CAS_MASK(1 downto 0);
RCA_ict(0):=’1’; -- byte M+L
CAS_DONE(1 downto 0):="11"; -- done
D_ict(15 downto 00):=RAM_D_W(15 downto 00);
end if;
when others =>
RCA_ict(13 downto 0):=RAM_COL(13 downto 0);
CAS_lat:=CAS_MASK;
CAS_DONE:="1111"; -- all bytes done
D_ict:=RAM_D_W;
end case;
-- address: | 0 1 2 3 | 4 5 6...
-- bytes: | U H M L | U H M...
-- CAS: | 3 2 1 0 | 3 2 1...
-- data bits:| 31-24 23-16 15-08 07-00 | ...
Subdiagram MEM_CYCLES: read or write RAM data
RAM_ADDR: address of read/write access
CAS_MASK: CAS mask
RAM_D_W: write data from current FIFO buffer pos.,
if necessary, up to 4 write cycles
are performed (HBW=32, MBW=8).
DATA_OUT: data read from the RAM
read: when RAM_READ=’1’ (HOST) or RAM_GREAD=’1’ (GPU)
write: when FIFO_IN/=FIFO_OUT (HOST)
or (RAM_GWRITE=’1’ and PRE_READ=’0’) (GPU)
rmw: when (RAM_GWRITE=’1’ and PRE_READ=’1’) (GPU)
Entry of
A: RCA_ict:=RAM_ROW;
T2
A: RAS_ict :=RAS_MASK;
LAST_RAS:=RAS_MASK;
ACS_ict :=ACS_MASK;
LAST_ACS:=ACS_MASK;
LAST_ROW:=RAM_ROW;
C: ANY_CYCLE=’1’
RAS1
T11
RAS2 CAS1
T3
T10 #0
entry
C: ANY_CYCLE=’1’
and LAST_ROW=RAM_ROW
and LAST_RAS=RAS_MASK
and LAST_ACS=ACS_MASK
T4
T1
T6 #1
A: CAS_ict:=CAS_lat;
if CAS_MASK="1111" then
if MEM_GWRITE=’1’ and
PRE_READ=’0’then
GPU_WRITE_DONE:=’1’;
-- request addr inc
-- (diagr. GPU_FIFO_W)
elsif MEM_GREAD=’1’ then
GREAD_END:=’1’;
-- read last data
GPU_READ_DONE:=’1’;
-- request addr inc
-- (diagr. GPU_FIFO_R)
end if;
end if;
Entry of
A: RAS_ict:="1111";
MWE_ict:=’1’;
MOE_ict:=’1’;
RCA_ict:=hi14;
DOE_ict:=lo32; -- input mode
cold_stb
C: ANY_CYCLE=’1’
-- if different ROW/RAS/ACS
or PEN=’0’
-- or timeout
T7
T12
hot_stb
T8
C: ANY_CYCLE=’0’ and PEN=’1’
A: MWE_ict:=’1’;
DOE_ict:=lo32; -- input mode
MOE_ict:=’1’;
RCA_ict:=hi14;
if MEM_READ=’1’ and READ_DONE=’1’ then
MEM_READ:=’0’;
end if;
C: ANY_CYCLE=’1’ and LAST_ROW=RAM_ROW
and LAST_RAS=RAS_MASK
and LAST_ACS=ACS_MASK
-- access same RAS address
and PEN=’1’
CAS2
T5
A: if CAS_MASK="1111" then
CAS_DONE:="0000";
if MEM_READ=’1’ then
READ_DONE:=’1’;
elsif FIFO_IN/=FIFO_OUT then
FIFO_OUT:=(FIFO_OUT+1) mod 8;
end if;
end if;
C: (ANY_CYCLE=’1’
and (LAST_ROW/=RAM_ROW
or LAST_RAS/=RAS_MASK
or LAST_ACS/=ACS_MASK))
-- access different RAS address
or PEN=’0’
A: if MEM_READ=’1’ and READ_DONE=’1’ then
MEM_READ:=’0’;
end if;
CAS3
RMW1
T9 #0
T15
CAS_END Exit of
A: CAS_ict:="1111";
T13
T16
C: MEM_RMW=’1’
A: MOE_ict:=’1’;
-- and exit action of CAS3
-- (read RAM data into DATA_OUT)
Subdiag Actions of
A: -- test only
FIFOIN_ot :=FIFO_IN mod 8;
FIFOOUT_ot :=FIFO_OUT mod 8;
CAS_MASK_ot :=CAS_MASK;
ANY_CYCLE_ot :=ANY_CYCLE;
MEM_GWRITE_ot :=MEM_GWRITE;
GPU_WNUM_ot :=GPU_WNUM mod 16;
MEM_GREAD_ot :=MEM_GREAD;
GPU_RNUM_ot :=GPU_RNUM mod 16;
PRE_READ_ot :=PRE_READ;
PRE_MASK_ot :=PRE_MASK;
Exit of
A: if MEM_READ=’1’ or MEM_GREAD=’1’
or (MEM_GWRITE=’1’ and PRE_READ=’1’) then
case MBW is
when "00" =>
case RCA_ict(1 downto 0) is
when "00" => DATA_OUT(31 downto 24)
:=MD_in(7 downto 0);
when "01" => DATA_OUT(23 downto 16)
:=MD_in(7 downto 0);
when "10" => DATA_OUT(15 downto 8)
:=MD_in(7 downto 0);
when "11" => DATA_OUT( 7 downto 0)
:=MD_in(7 downto 0);
end case;
when "01" =>
case RCA_ict(0) is
when ’0’ => DATA_OUT(31 downto 16)
:=MD_in(15 downto 0);
when ’1’ => DATA_OUT(15 downto 0)
:=MD_in(15 downto 0);
end case;
when others =>
DATA_OUT:=MD_in;
end case;
end if;
GREAD_END:=’0’;
A: GPU_WRITE_DONE:=’1’;
-- output modified data:
case MBW is
when "00" =>
case RCA_ict(1 downto 0) is
when "00" => D_ict(7 downto 0):=RAM_D_W(31 downto 24);
when "01" => D_ict(7 downto 0):=RAM_D_W(23 downto 16);
when "10" => D_ict(7 downto 0):=RAM_D_W(15 downto 08);
when "11" => D_ict(7 downto 0):=RAM_D_W(07 downto 00);
end case;
when "01" =>
case RCA_ict(0) is
when ’0’ => D_ict(15 downto 00):=RAM_D_W(31 downto 16);
when ’1’ => D_ict(15 downto 00):=RAM_D_W(15 downto 00);
end case;
when others =>
D_ict:=RAM_D_W;
end case;
T14
RMW3
RMW2
A: MWE_ict:=’0’;
-- write enable
MEM_RMW:=’0’;
Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang D.2
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