DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Abbildung 90: Speedchart-Diagramm TIM/CONTROL/TIM ACCESS
TIM_ACCESS
C: FIFO_IN=FIFO_OUT
A: MEM_READ:=’1’;
-- start read when
-- FIFO is empty
T12 #1
C: RS_lat=’1’ and
(DS_in=’0’ or RS_MUX=’0’)
A: AD_oe:=hi32; -- oe enable
A_READ :=AD_lat;
CAS_READ:=BS_lat;
READ_DONE:=’0’;
if FIFO_IN=FIFO_OUT then
MEM_READ:=’1’;
end if;
-- wait if FIFO not empty
C: AS_in=’0’
A: -- latch input lines
A: RDY_out:=bnot RS_Rdy;
-- ready active
C: READ_DONE=’1’
mem_read
T11
T9 #0
read
T7
RDY
T8
reg_read
T14
ADS_lat :=AD_in(8 downto 2); -- register address
AD_lat :=AD_in; -- full address
D_lat :=AD_in; -- write data if nonmux
RS_lat :=RS_in; -- register select
-- get or calculate BS3..BS0 byte select signals
C: RS_lat=’0’ and
(DS_in=’0’ or
RS_MUX=’0’)
A: AD_oe:=hi32;
-- output enable
T1
C: HWE_in=’1’
wt_end
if HBW="00" then -- convert 8 -> 32 bit
case AD_in(1 downto 0) is
when "00" => BS_lat:="0111";
when "01" => BS_lat:="1011";
when "10" => BS_lat:="1101";
when "11" => BS_lat:="1110";
end case;
elsif HBW="01" then -- convert 16 -> 32 bit
case AD_in(0) is
when ’0’ => BS_lat(3 downto 2):=BS_in(1 downto 0);
BS_lat(1 downto 0):="11";
when ’1’ => BS_lat(3 downto 2):="11";
BS_lat(1 downto 0):=BS_in(1 downto 0);
end case;
else -- 32 bit
BS_lat:=BS_in;
end if;
T5
AS
wait_AS
A: if FASTRDY=’0’ then
RDY_out:=bnot RS_Rdy;
-- ready active
end if;
T17
T15
w_done
T4
T6
T13
entry
reg_write
T3
C: RS_lat=’0’
DS
write
C: HWE_in=’0’
T2
T10
C: AS_in=’1’
A: RDY_out:=RS_Rdy;
-- ready inactive
-- enable next access
C: RS_lat=’1’ and
FIFO_IN/=
(FIFO_OUT+4) mod 8
A: -- write RAM data
-- into FIFO buffer
case (FIFO_IN mod 4) is
when 0 =>
CAS_FIFO0:=BS_lat;
A_FIFO0 :=AD_lat;
D_FIFO0 :=DATA_IN;
when 1 =>
CAS_FIFO1:=BS_lat;
A_FIFO1 :=AD_lat;
D_FIFO1 :=DATA_IN;
when 2 =>
CAS_FIFO2:=BS_lat;
A_FIFO2 :=AD_lat;
D_FIFO2 :=DATA_IN;
when 3 =>
CAS_FIFO3:=BS_lat;
A_FIFO3 :=AD_lat;
D_FIFO3 :=DATA_IN;
end case;
FIFO_IN:=(FIFO_IN+1) mod 8;
C: DS_in=’0’ or RS_MUX=’0’
A: if FASTRDY=’1’ then
RDY_out:=bnot RS_Rdy;
-- ready active
end if;
Subdiag Actions of
A: -- convert read/write data from HBW bus size to 32 bit
if HBW="00" then -- 32 -> 8 bit
if RS_MUX=’1’ then
DATA_IN(31 downto 24):=AD_in(7 downto 0); -- upper byte
DATA_IN(23 downto 16):=AD_in(7 downto 0); -- higher byte
DATA_IN(15 downto 08):=AD_in(7 downto 0); -- middle byte
DATA_IN(07 downto 00):=AD_in(7 downto 0); -- lower byte
else
DATA_IN(31 downto 24):=D_lat(7 downto 0); -- upper byte
DATA_IN(23 downto 16):=D_lat(7 downto 0); -- higher byte
DATA_IN(15 downto 08):=D_lat(7 downto 0); -- middle byte
DATA_IN(07 downto 00):=D_lat(7 downto 0); -- lower byte
end if;
-- 8 -> 32 bit
case AD_lat(1 downto 0) is
when "00" => AD_out(7 downto 0):=DATA_OUT(31 downto 24);
D_out(7 downto 0) :=DATA_OUT(31 downto 24);
when "01" => AD_out(7 downto 0):=DATA_OUT(23 downto 16);
D_out(7 downto 0) :=DATA_OUT(23 downto 16);
when "10" => AD_out(7 downto 0):=DATA_OUT(15 downto 08);
D_out(7 downto 0) :=DATA_OUT(15 downto 08);
when "11" => AD_out(7 downto 0):=DATA_OUT(07 downto 00);
D_out(7 downto 0) :=DATA_OUT(07 downto 00);
end case;
elsif HBW="01" then -- 32 -> 16 bit
if RS_MUX=’1’ then
DATA_IN(31 downto 16):=AD_in(15 downto 0); -- high 2 bytes
DATA_IN(15 downto 00):=AD_in(15 downto 0); -- low 2 bytes
else
DATA_IN(31 downto 16):=D_lat(15 downto 0); -- high 2 bytes
DATA_IN(15 downto 00):=D_lat(15 downto 0); -- low 2 bytes
end if;
-- 16 -> 32 bit
case AD_lat(0) is
when ’0’ => AD_out(15 downto 0):=DATA_OUT(31 downto 16);
D_out(15 downto 0) :=DATA_OUT(31 downto 16);
when ’1’ => AD_out(15 downto 0):=DATA_OUT(15 downto 00);
D_out(15 downto 0) :=DATA_OUT(15 downto 00);
end case;
else
if RS_MUX=’1’ then
if NUBUS=’1’ then
DATA_IN(07 downto 00):=AD_in(31 downto 24); -- reverse
DATA_IN(15 downto 08):=AD_in(23 downto 16); -- byte
DATA_IN(23 downto 16):=AD_in(15 downto 08); -- order
DATA_IN(31 downto 24):=AD_in(07 downto 00); -- for data
else
DATA_IN:=AD_in; -- 32 bit
end if;
else
DATA_IN:=D_lat; -- 32 bit
end if;
if NUBUS=’1’ then
AD_out(07 downto 00):=DATA_OUT(31 downto 24); -- reverse
AD_out(15 downto 08):=DATA_OUT(23 downto 16); -- byte
AD_out(23 downto 16):=DATA_OUT(15 downto 08); -- order
AD_out(31 downto 24):=DATA_OUT(07 downto 00); -- for data
else
AD_out:=DATA_OUT; -- 32 bit
end if;
D_out:=DATA_OUT; -- 32 bit
end if;
Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang D.2
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