DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diagram Variables:
-- Variables of Diagram VIDEO
-- registers
HCOUNT: int16:=0;
VCOUNT: int16:=0;
HTOTAL: int16:=0;
HESYNC: int16:=0;
HSBLNK: int16:=0;
HEBLNK: int16:=0;
HESERR: int16:=0;
VTOTAL: int16:=0;
VESYNC: int16:=0;
VSBLNK: int16:=0;
VEBLNK: int16:=0;
LINTV: int16:=0;
SETHCNT:int16:=0;
SETVCNT:int16:=0;
DPYSTRT: int27:=0; -- hi 27 bits, lo 5 bits=0
DPYHELP(27): logic; -- equals DPYSTRT(31 downto 5)
DPYINC: int27:=0; -- hi 27 bits, lo 5 bits=0
YZ(3): logic:="000"; -- Y zoom factor
XZ(3): logic:="000"; -- X zoom factor
RLE: logic:=’0’; -- reload enable
SRE: logic:=’0’; -- split reload enable
SRL(2): logic:="00"; -- shift reg length
MBW(2): logic:="00"; -- memory bus width
NTSC: logic:=’0’; -- ’1’=NTSC, ’0’=PAL
ILE: logic:=’0’; -- interlaced enable
VEN: logic:=’0’; -- video enable
TEST: logic:=’0’; -- ’1’: counter test
CSD: logic:=’0’; -- CSYNC direction
HSD: logic:=’0’; -- HSYNC direction
VSD: logic:=’0’; -- VSYNC direction
RF(3): logic:="000"; -- refresh rate
FASTRAM:logic:=’0’; -- ’1’=perform fast RAS cycles
DPYNEXT: int27:=0; -- hi 27 bits, lo 5 bits=0
DPYNEXTV(27): logic;
-- reload control interface
MLRAT10: logic:=’0’; -- attent.: midl. rel. -10
MLRAT6: logic:=’0’; -- attent.: midl. rel. -6
HC_MLR10: int16:=0; -- HCOUNT value at rel -10
HC_MLR6: int16:=0; -- HCOUNT value at rel -6
HC_MEN10: logic:=’0’; -- ’1’=enable HC_MLR10
HC_MEN6: logic:=’0’; -- ’1’=enable HC_MLR6
RELOAD: logic:=’0’; -- 1=do line end reload
RELAT10: logic:=’0’; -- attent.: newl. rel. -10
RELAT6: logic:=’0’; -- attent.: newl. rel. -6
RELAREA: logic:=’0’;
MSC_reload: logic:=’1’; -- ’0’: pulse after reload
Clk_Div: logic; -- ’0’: MSC = VClk
-- video components
HBLANK: logic:=’0’;
VBLANK: logic:=’0’;
-- VRAM internal control signals
RCA_itv(12): logic:=hi12;
DIN_itv(32): logic:=hi32;
MOE_itv: logic:=’1’;
MWE_itv: logic:=’1’;
MSF_itv: logic:=’0’;
RAS_itv(4): logic:="1111";
CAS_itv(4): logic:="1111";
MSC_itv: logic;
LD_itv: logic;
-- substitutes for ’changing (for diagram SYNC)
HSin_old: logic:=’1’;
HSin_new: logic:=’1’;
VSin_old: logic:=’1’;
VSin_new: logic:=’1’;
CSin_old: logic:=’1’;
CSin_new: logic:=’1’;
ILE_last: logic:=’0’;
CSD_last: logic:=’0’;
HSD_last: logic:=’0’;
VSD_last: logic:=’0’;
HTOTAL_last: int16:=0;
VTOTAL_last: int16:=0;
Abbildung 44: Variablen im Diagramm VIDEO
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang C.2
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