DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Abbildung 62: Speedchart-Diagramm VIDEO/RELOAD/RL RAM/NEWL REL
NEWL_REL
entry
T1
S1
T2
S2
T4
A: -- 1st cycle of newline reload
A: -- 2nd cycle
A: -- 3rd cycle
RAS_itv:="1111";
CAS_itv:="1111";
RAS_itv:="1110";
RCA_itv:=DPYNEXTV(11 downto 0);
MWE_itv:=’1’;
-- calculate # of reloads necessary in next line
-- calculate HCOUNT value for start of
MOE_itv:=’0’;
-- CALC_NRL: SRE=’0’: number of non-split reloads
-- MLRAT6 and MLRAT10 midl. rel. attention signals
MSF_itv:=’0’;
-- SRE=’1’: # of split low half SR rel.
-- CALC_NRH: SRE=’0’: no function
-- and MLRAT5 midline reload start signal
-- and calculation of SUM_TAP_ELL
-- SRE=’1’: # of split high half SR rel.
if HC_MEN5=’1’ then
-- and calculation of TAPCNT (TAP position)
if HC_MLR>=5 then
if SUM_TE_A=’1’ then
HC_MLR5:=HC_MLR-5;
case SRL is
CALC_NRL:=(CALC_ELL_SFT + 1) mod 256;
else
when "00" => -- SRL: 256 words
else
HC_MLR5:=(HC_MLR+HTOTAL-4) mod 65536;
RCA_itv:=DPYNEXTV(19 downto 8);
CALC_NRL:=CALC_ELL_SFT;
end if;
ROWCNT:=(DPYNEXT shr 8) mod 4096;
TAPCNT:=(DPYNEXT mod 256) + 0x700;
end if;
end if;
SUM_TAP_ELL:=(DPYNEXT mod 256) + (CALC_ELL mod 256);
CALC_NRH:=(CALC_ELL_SFT + 1) mod 256
if HC_MEN6=’1’ then
when SUM_TE_A=’1’ and SUM_TE_B=’1’
if HC_MLR>=11 then
when "01" => -- SRL: 512 words
else (CALC_ELL_SFT - 1)
HC_MLR6:=HC_MLR-11;
RCA_itv:=DPYNEXTV(20 downto 9);
when SUM_TE_A=’0’ and SUM_TE_B=’0’
else
ROWCNT:=(DPYNEXT shr 9) mod 4096;
and CALC_ELL_SFT/=0
HC_MLR6:=(HC_MLR+HTOTAL-10) mod 65536;
TAPCNT:=(DPYNEXT mod 512) + 0x600;
else CALC_ELL_SFT;
end if;
SUM_TAP_ELL:=(DPYNEXT mod 512) + (CALC_ELL mod 512);
-- calculate HCOUNT value at point of midline reload
end if;
when "10" => -- SRL: 1024 words
if HC_MEN10=’1’ then
RCA_itv:=DPYNEXTV(21 downto 10);
case MSC_SFT is
if HC_MLR>=15 then
ROWCNT:=(DPYNEXT shr 10) mod 4096;
when 0 => HC_MLR:=(HEBLNK+(0x800-TAPCNT)) mod 65536;
HC_MLR10:=HC_MLR-15;
TAPCNT:=(DPYNEXT mod 1024) + 0x400;
when 1 => HC_MLR:=(HEBLNK+(0x800-TAPCNT) shl 1) mod 65536;
else
SUM_TAP_ELL:=(DPYNEXT mod 1024) + (CALC_ELL mod 1024);
when 2 => HC_MLR:=(HEBLNK+(0x800-TAPCNT) shl 2) mod 65536;
HC_MLR10:=(HC_MLR+HTOTAL-14) mod 65536;
when 3 => HC_MLR:=(HEBLNK+(0x800-TAPCNT) shl 3) mod 65536;
end if;
when "11" => -- SRL: 2048 words
when 4 => HC_MLR:=(HEBLNK+(0x800-TAPCNT) shl 4) mod 65536;
end if;
RCA_itv:=DPYNEXTV(22 downto 11);
when 5 => HC_MLR:=(HEBLNK+(0x800-TAPCNT) shl 5) mod 65536;
ROWCNT:=(DPYNEXT shr 11) mod 4096;
TAPCNT:=DPYNEXT mod 2048;
end case;
SUM_TAP_ELL:=(DPYNEXT mod 2048) + (CALC_ELL mod 2048);
-- determine if HCOUNT has to be regarded to
end case;
-- generate midline reload attention signals
-- disable HC_MLR6 and HC_MLR10 signals
case MSC_SFT is
when 0 => if TAPCNT>0x7FB then -- 0x800 -5
HC_MEN5 :=’0’;
HC_MEN5:=’1’;
HC_MEN6 :=’0’;
end if;
HC_MEN10:=’0’;
if TAPCNT>0x7F5 then -- 0x800 -11 (5+6)
HC_MEN6:=’1’;
end if;
if TAPCNT>0x7F1 then -- 0x800 -15 (5+10)
HC_MEN10:=’1’;
end if;
when 1 => if TAPCNT>0x7FD then -- 0x800 -(5/2 up)
HC_MEN5:=’1’;
end if;
if TAPCNT>0x7FA then -- 0x800 -(11/2 up)
HC_MEN6:=’1’;
end if;
if TAPCNT>0x7F8 then -- 0x800 -(15/2 up)
HC_MEN10:=’1’;
end if;
when 2 => if TAPCNT=0x7FF then -- 0x800 -(5/4 up)
HC_MEN5:=’1’;
end if;
if TAPCNT>0x7FD then -- 0x800 -(11/4 up)
HC_MEN6:=’1’;
end if;
if TAPCNT>0x7FC then -- 0x800 -(15/4 up)
HC_MEN10:=’1’;
end if;
when 3 => if TAPCNT=0x7FF then -- 0x800 -(11/8 up)
HC_MEN6:=’1’;
HC_MEN10:=’1’; -- 0x800 -(15/8 up)
end if;
end case;
T6
T7
T3
T5
S3
S4
S5
S6
exit
A: -- 4th cycle
CAS_itv:="0000";
A: -- 5th cycle
RCA_itv:=0xFFF;
MOE_itv:=’1’;
A: -- 6th cycle
RAS_itv:="1111";
CAS_itv:="1111";
MSC_reload:=’0’; -- MSC low pulse
-- after newline reload
A: MSC_reload:=’1’;
Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang C.2
Seite 95