DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Diagram Variables:
-- Variables of Diagram VRAM_4_258
RAS_WE: logic:=’0’; -- MWE at falling edge of RAS
RAS_SF: logic:=’0’; -- MSF at falling edge of RAS
RAS_SE: logic:=’0’; -- MSE at falling edge of RAS
RAS_OE: logic:=’0’; -- MOE at falling edge of RAS
flag: logic:=’0’;
DIR_input: logic:=’1’; -- 1=input mode,
-- last transfer was write
DoLoad: logic:=’0’; -- 0=load SR counter
MWE_old: logic:=’0’;
MWE_falling: logic;
MSC_old: logic:=’1’;
MSC_rising: logic;
CAS_old: logic:=’0’;
CAS_falling: logic;
Column(9): logic:=lo9;
Row(9): logic:=lo9;
WM1(32): logic:=lo32; -- write mask
Color(32): logic:=lo32; -- color register
Anhang C.2
Seite 85
TAP(9): logic:=lo9; -- TAP
LTAP(9): logic:="000000000"; -- TAP for low half SR
HTAP(9): logic:="100000000"; -- TAP for high half SR
SRCNT: integer(0 to 511):=0; -- SR counter
SRCNTV(9): logic; -- SR counter as a vector
CLRow(9): logic:=lo9; -- current SR row low half
CHRow(9): logic:=lo9; -- current SR row high half
NRow(9): logic:=lo9; -- next SR row
dummy2: logic:=’1’;
Abbildung 52: Variablen im Diagramm VIDEO/VRAM