DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
GPU_FIFO_R
entry
T3
T1
S1
S2
T4
T2
A: -- write data read from memory into GPU fifo buffer
-- (write DATA_OUT via BIT_SHIFT, S_HI_LW/S_LO_LW)
-- and increment LW address & buffer position
if PBV=’0’ then -- left to right
case GPU_FIFO_IN is
when 0 => D_GPU_FIFO8:=D_GPU_FIFO8 bor S_HI_LW;
D_GPU_FIFO0:=S_LO_LW;
when 1 => D_GPU_FIFO0:=D_GPU_FIFO0 bor S_HI_LW;
D_GPU_FIFO1:=S_LO_LW;
when 2 => D_GPU_FIFO1:=D_GPU_FIFO1 bor S_HI_LW;
D_GPU_FIFO2:=S_LO_LW;
when 3 => D_GPU_FIFO2:=D_GPU_FIFO2 bor S_HI_LW;
D_GPU_FIFO3:=S_LO_LW;
when 4 => D_GPU_FIFO3:=D_GPU_FIFO3 bor S_HI_LW;
D_GPU_FIFO4:=S_LO_LW;
when 5 => D_GPU_FIFO4:=D_GPU_FIFO4 bor S_HI_LW;
D_GPU_FIFO5:=S_LO_LW;
when 6 => D_GPU_FIFO5:=D_GPU_FIFO5 bor S_HI_LW;
D_GPU_FIFO6:=S_LO_LW;
when 7 => D_GPU_FIFO6:=D_GPU_FIFO6 bor S_HI_LW;
D_GPU_FIFO7:=S_LO_LW;
when 8 => D_GPU_FIFO7:=D_GPU_FIFO7 bor S_HI_LW;
D_GPU_FIFO8:=S_LO_LW;
end case;
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
GPU_FIFO_IN:=GPU_FIFO_IN+1 when GPU_FIFO_IN/=8 else 0;
else -- right to left
case GPU_FIFO_IN is
when 8 => D_GPU_FIFO0:=D_GPU_FIFO0 bor S_LO_LW;
D_GPU_FIFO8:=S_HI_LW;
when 7 => D_GPU_FIFO8:=D_GPU_FIFO8 bor S_LO_LW;
D_GPU_FIFO7:=S_HI_LW;
when 6 => D_GPU_FIFO7:=D_GPU_FIFO7 bor S_LO_LW;
D_GPU_FIFO6:=S_HI_LW;
when 5 => D_GPU_FIFO6:=D_GPU_FIFO6 bor S_LO_LW;
D_GPU_FIFO5:=S_HI_LW;
when 4 => D_GPU_FIFO5:=D_GPU_FIFO5 bor S_LO_LW;
D_GPU_FIFO4:=S_HI_LW;
when 3 => D_GPU_FIFO4:=D_GPU_FIFO4 bor S_LO_LW;
D_GPU_FIFO3:=S_HI_LW;
when 2 => D_GPU_FIFO3:=D_GPU_FIFO3 bor S_LO_LW;
D_GPU_FIFO2:=S_HI_LW;
when 1 => D_GPU_FIFO2:=D_GPU_FIFO2 bor S_LO_LW;
D_GPU_FIFO1:=S_HI_LW;
when 0 => D_GPU_FIFO1:=D_GPU_FIFO1 bor S_LO_LW;
D_GPU_FIFO0:=S_HI_LW;
end case;
GPU_FIFO_IN:=GPU_FIFO_IN-1 when GPU_FIFO_IN/=0 else 8;
end if;
S3
C: GPU_READ_DONE=’1’
A: -- decrement RNUM (number of longwords to go)
-- and check for end of line
GPU_READ_DONE:=’0’;
if PBV=’0’ then -- left to right
if SADRLW_C=SADRLW_R then
GPU_RNUM:=15; -- end of line, abort read-in phase
GPU_READ:=’0’;
else
if GPU_RNUM=1 then
GPU_READ:=’0’; -- all LW’s done
end if;
GPU_RNUM:=GPU_RNUM-1;
end if;
SADRLW_C:=SADRLW_C+1; -- next source LW address
else -- right to left
if SADRLW_C=SADRLW_L then
GPU_RNUM:=15; -- end of line, abort read-in phase
GPU_READ:=’0’;
else
if GPU_RNUM=1 then
GPU_READ:=’0’; -- all LW’s done
end if;
GPU_RNUM:=GPU_RNUM-1;
end if;
SADRLW_C:=SADRLW_C-1; -- next (prev.) source LW address
end if;
Abbildung 99: Speedchart-Diagramm TIM/CONTROL/MEM ACCESS/GPU FIFO R
Anhang D.2
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