DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diagram Variables:
-- Variables of Diagram CONTROL
-- address, data & control for RAM access
AD_lat(32): logic;
D_lat(32): logic;
ADS_lat(7): logic;
RS_lat: logic;
BS_lat(4): logic;
CAS_lat(4): logic;
STAT_CLR: logic:=’0’;
-- host input / output data
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
DATA_IN(32): logic; -- host write data
DATA_OUT(32): logic:=lo32; -- read data from TIM
-- ram write data FIFO buffer, 4*32 bits
-- XXX_FIFO0 = position 0
D_FIFO0(32): logic; -- write data
D_FIFO1(32): logic;
D_FIFO2(32): logic;
D_FIFO3(32): logic;
RAM_D_W(32): logic; -- write data of output position
A_FIFO0(32): logic; -- address
A_FIFO1(32): logic;
A_FIFO2(32): logic;
A_FIFO3(32): logic;
RAM_ADDR(32): logic; -- address of output position
CAS_FIFO0(4): logic; -- CAS mask (BS byte select)
CAS_FIFO1(4): logic;
CAS_FIFO2(4): logic;
CAS_FIFO3(4): logic;
CAS_MASK(4): logic; -- CAS mask of output position
-- FIFO control
signal FIFO_IN: int3:=0; -- FIFO input position (low 2 bits)
--^^^^ SIGNAL makes the design behave FSM-like
FIFO_OUT: int3:=0; -- FIFO output position (low 2 bits)
CAS_DONE(4): logic:="0000"; -- ’1’=byte already written
LAST_ROW(14): logic; -- page mode last RAM row
LAST_RAS(4): logic; -- page mode last RAS select signals
LAST_ACS(4): logic; -- page mode last ACS select signals
-- RAM read control
A_READ(32): logic; -- read address
CAS_READ(4): logic; -- read byte mask
READ_DONE: logic;
MEM_READ: logic:=’0’; -- ’1’=perform RAM read
-- RAS address calculation
RS_A(2): logic; -- value of "RAS bank select" address bits
RAS_MASK(4): logic; -- decoded RS_A bits
MOX(3): logic; -- RAS address selector of selected bank
RAM_ROW(14): logic; -- accessed RAM row
RAM_COL(14): logic; -- accessed (1st) RAM column
-- ACS bank calculation
AS_A(2): logic; -- value of "ACS bank select" address bits
ACS_MASK(4): logic; -- decoded AS_A bits
-- source read data FIFO buffer and barrel shifter
S_HI_LW(32): logic; -- high longword of shifted source data
S_LO_LW(32): logic; -- low longword of shifted source data
DBMASK_L(32): logic; -- data bit mask at line start
DBMASK_R(32): logic; -- data bit mask at line end
Abbildung 89: Variablen im Diagramm TIM/CONTROL
Anhang D.2
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