DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
BIT_SHIFT
Subdiag Actions of
V: BOTH_LW(64): logic;
A: -- fit DATA_OUT longword into (S_HI_LW / S_LO_LW)
-- starting at bit number (DBOS_L-SBOS_L)
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
case ((DBOS_L+32)-SBOS_L) mod 32 is -- +32 for speedchart
when 0 => BOTH_LW(63 downto 32):=DATA_OUT;
BOTH_LW(31 downto 00):=lo32;
when 1 => BOTH_LW(63):=’0’;
BOTH_LW(62 downto 31):=DATA_OUT;
BOTH_LW(30 downto 00):="0000000000000000000000000000000";
when 2 => BOTH_LW(63 downto 62):="00";
BOTH_LW(61 downto 30):=DATA_OUT;
BOTH_LW(29 downto 00):="000000000000000000000000000000";
when 3 => BOTH_LW(63 downto 61):="000";
BOTH_LW(60 downto 29):=DATA_OUT;
BOTH_LW(28 downto 00):="00000000000000000000000000000";
when 4 => BOTH_LW(63 downto 60):="0000";
BOTH_LW(59 downto 28):=DATA_OUT;
BOTH_LW(27 downto 00):="0000000000000000000000000000";
when 5 => BOTH_LW(63 downto 59):="00000";
BOTH_LW(58 downto 27):=DATA_OUT;
BOTH_LW(26 downto 00):="000000000000000000000000000";
when 6 => BOTH_LW(63 downto 58):="000000";
BOTH_LW(57 downto 26):=DATA_OUT;
BOTH_LW(25 downto 00):="00000000000000000000000000";
when 7 => BOTH_LW(63 downto 57):="0000000";
BOTH_LW(56 downto 25):=DATA_OUT;
BOTH_LW(24 downto 00):="0000000000000000000000000";
when 8 => BOTH_LW(63 downto 56):="00000000";
BOTH_LW(55 downto 24):=DATA_OUT;
BOTH_LW(23 downto 00):="000000000000000000000000";
when 9 => BOTH_LW(63 downto 55):="000000000";
BOTH_LW(54 downto 23):=DATA_OUT;
BOTH_LW(22 downto 00):="00000000000000000000000";
when 10 => BOTH_LW(63 downto 54):="0000000000";
BOTH_LW(53 downto 22):=DATA_OUT;
BOTH_LW(21 downto 00):="0000000000000000000000";
when 11 => BOTH_LW(63 downto 53):="00000000000";
BOTH_LW(52 downto 21):=DATA_OUT;
BOTH_LW(20 downto 00):="000000000000000000000";
when 12 => BOTH_LW(63 downto 52):="000000000000";
BOTH_LW(51 downto 20):=DATA_OUT;
BOTH_LW(19 downto 00):="00000000000000000000";
when 13 => BOTH_LW(63 downto 51):="0000000000000";
BOTH_LW(50 downto 19):=DATA_OUT;
BOTH_LW(18 downto 00):="0000000000000000000";
when 14 => BOTH_LW(63 downto 50):="00000000000000";
BOTH_LW(49 downto 18):=DATA_OUT;
BOTH_LW(17 downto 00):="000000000000000000";
when 15 => BOTH_LW(63 downto 49):="000000000000000";
BOTH_LW(48 downto 17):=DATA_OUT;
BOTH_LW(16 downto 00):="00000000000000000";
when 16 => BOTH_LW(63 downto 48):="0000000000000000";
BOTH_LW(47 downto 16):=DATA_OUT;
BOTH_LW(15 downto 00):="0000000000000000";
when 17 => BOTH_LW(63 downto 47):="00000000000000000";
BOTH_LW(46 downto 15):=DATA_OUT;
BOTH_LW(14 downto 00):="000000000000000";
when 18 => BOTH_LW(63 downto 46):="000000000000000000";
BOTH_LW(45 downto 14):=DATA_OUT;
BOTH_LW(13 downto 00):="00000000000000";
when 19 => BOTH_LW(63 downto 45):="0000000000000000000";
BOTH_LW(44 downto 13):=DATA_OUT;
BOTH_LW(12 downto 00):="0000000000000";
when 20 => BOTH_LW(63 downto 44):="00000000000000000000";
BOTH_LW(43 downto 12):=DATA_OUT;
BOTH_LW(11 downto 00):="000000000000";
when 21 => BOTH_LW(63 downto 43):="000000000000000000000";
BOTH_LW(42 downto 11):=DATA_OUT;
BOTH_LW(10 downto 00):="00000000000";
when 22 => BOTH_LW(63 downto 42):="0000000000000000000000";
BOTH_LW(41 downto 10):=DATA_OUT;
BOTH_LW(09 downto 00):="0000000000";
when 23 => BOTH_LW(63 downto 41):="00000000000000000000000";
BOTH_LW(40 downto 09):=DATA_OUT;
BOTH_LW(08 downto 00):="000000000";
when 24 => BOTH_LW(63 downto 40):="000000000000000000000000";
BOTH_LW(39 downto 08):=DATA_OUT;
BOTH_LW(07 downto 00):="00000000";
when 25 => BOTH_LW(63 downto 39):="0000000000000000000000000";
BOTH_LW(38 downto 07):=DATA_OUT;
BOTH_LW(06 downto 00):="0000000";
when 26 => BOTH_LW(63 downto 38):="00000000000000000000000000";
BOTH_LW(37 downto 06):=DATA_OUT;
BOTH_LW(05 downto 00):="000000";
when 27 => BOTH_LW(63 downto 37):="000000000000000000000000000";
BOTH_LW(36 downto 05):=DATA_OUT;
BOTH_LW(04 downto 00):="00000";
when 28 => BOTH_LW(63 downto 36):="0000000000000000000000000000";
BOTH_LW(35 downto 04):=DATA_OUT;
BOTH_LW(03 downto 00):="0000";
when 29 => BOTH_LW(63 downto 35):="00000000000000000000000000000";
BOTH_LW(34 downto 03):=DATA_OUT;
BOTH_LW(02 downto 00):="000";
when 30 => BOTH_LW(63 downto 34):="000000000000000000000000000000";
BOTH_LW(33 downto 02):=DATA_OUT;
BOTH_LW(01 downto 00):="00";
when 31 => BOTH_LW(63 downto 33):="0000000000000000000000000000000";
BOTH_LW(32 downto 01):=DATA_OUT;
BOTH_LW(0):=’0’;
end case;
S_HI_LW:=BOTH_LW(63 downto 32);
S_LO_LW:=BOTH_LW(31 downto 00);
Abbildung 96: Speedchart-Diagramm TIM/CONTROL/MEM ACCESS/BIT SHIFT
Anhang D.2
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