DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Diagram Variables:
-- Variables of Diagram GR_CPU
SADR_P_HI: integer:=0; -- 1st comp. of SYADR * R_SINC
SADR_P_LO: integer:=0; -- 2nd comp. of SYADR * R_SINC
SADR_P: integer:=0; -- (SYADR * R_SINC) + SXADR
SY_P_HI: integer:=0; -- 1st comp. of (DY-1) * R_SINC
SY_P_LO: integer:=0; -- 2nd comp. of (DY-1) * R_SINC
SY_P: integer:=0; -- (DY-1) * R_SINC
DADR_P_HI: integer:=0; -- 1st comp. of DYADR * R_DINC
DADR_P_LO: integer:=0; -- 2nd comp. of DYADR * R_DINC
DADR_P: integer:=0; -- (DYADR * R_DINC) + DXADR
DY_P_HI: integer:=0; -- 1st comp. of (DY-1) * R_DINC
DY_P_LO: integer:=0; -- 2nd comp. of (DY-1) * R_DINC
DY_P: integer:=0; -- (DY-1) * R_DINC
Anhang D.2
Seite 133
SADRL_L: integer:=0; -- source first line leftmost pixel
SADRL_R: integer:=0; -- source first line rightmost pixel
DADRL_L: integer:=0; -- dest. first line leftmost pixel
DADRL_R: integer:=0; -- dest. first line rightmost pixel
XS_viol: logic; -- window area violation X start
XE_viol: logic; -- window area violation X end
YS_viol: logic; -- window area violation Y start
YE_viol: logic; -- window area violation Y end
LINCNT: int16:=0; -- "lines left" counter for PixBLT
constant C_FILL_L(8): logic:=0x21;
constant C_FILL_XY(8): logic:=0x22;
constant C_PixBLT_L(8): logic:=0x31;
constant C_PixBLT_XY(8): logic:=0x32;
constant C_CLIP(8): logic:=0x40;
Abbildung 103: Variablen im Diagramm TIM/GR CPU