DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
SY_SPLIT
Subdiag Actions of
A: -- multiplication of (DY-1) and R_SINC:
-- assume the bits a and b are set in R_SINC,
-- then SY_P_HI:= (DY-1) shl a;
-- and SY_P_LO:= (DY-1) shl b;
--
-- SY_P:=(DY-1) * R_SINC;
if R_SINC(15)=’1’ then
SY_P_HI:=(DY-1) shl 15;
elsif R_SINC(14)=’1’ then
SY_P_HI:=(DY-1) shl 14;
elsif R_SINC(13)=’1’ then
SY_P_HI:=(DY-1) shl 13;
elsif R_SINC(12)=’1’ then
SY_P_HI:=(DY-1) shl 12;
elsif R_SINC(11)=’1’ then
SY_P_HI:=(DY-1) shl 11;
elsif R_SINC(10)=’1’ then
SY_P_HI:=(DY-1) shl 10;
elsif R_SINC(9)=’1’ then
SY_P_HI:=(DY-1) shl 9;
elsif R_SINC(8)=’1’ then
SY_P_HI:=(DY-1) shl 8;
elsif R_SINC(7)=’1’ then
SY_P_HI:=(DY-1) shl 7;
elsif R_SINC(6)=’1’ then
SY_P_HI:=(DY-1) shl 6;
elsif R_SINC(5)=’1’ then
SY_P_HI:=(DY-1) shl 5;
elsif R_SINC(4)=’1’ then
SY_P_HI:=(DY-1) shl 4;
elsif R_SINC(3)=’1’ then
SY_P_HI:=(DY-1) shl 3;
elsif R_SINC(2)=’1’ then
SY_P_HI:=(DY-1) shl 2;
elsif R_SINC(1)=’1’ then
SY_P_HI:=(DY-1) shl 1;
else
SY_P_HI:=(DY-1);
end if;
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
if R_SINC(0)=’1’ and R_SINC/="0000000000000001" then
SY_P_LO:=(DY-1);
elsif R_SINC(1)=’1’ and R_SINC(15 downto 1)/="000000000000001" then
SY_P_LO:=(DY-1) shl 1;
elsif R_SINC(2)=’1’ and R_SINC(15 downto 2)/="00000000000001" then
SY_P_LO:=(DY-1) shl 2;
elsif R_SINC(3)=’1’ and R_SINC(15 downto 3)/="0000000000001" then
SY_P_LO:=(DY-1) shl 3;
elsif R_SINC(4)=’1’ and R_SINC(15 downto 4)/="000000000001" then
SY_P_LO:=(DY-1) shl 4;
elsif R_SINC(5)=’1’ and R_SINC(15 downto 5)/="00000000001" then
SY_P_LO:=(DY-1) shl 5;
elsif R_SINC(6)=’1’ and R_SINC(15 downto 6)/="0000000001" then
SY_P_LO:=(DY-1) shl 6;
elsif R_SINC(7)=’1’ and R_SINC(15 downto 7)/="000000001" then
SY_P_LO:=(DY-1) shl 7;
elsif R_SINC(8)=’1’ and R_SINC(15 downto 8)/="00000001" then
SY_P_LO:=(DY-1) shl 8;
elsif R_SINC(9)=’1’ and R_SINC(15 downto 9)/="0000001" then
SY_P_LO:=(DY-1) shl 9;
elsif R_SINC(10)=’1’ and R_SINC(15 downto 10)/="000001" then
SY_P_LO:=(DY-1) shl 10;
elsif R_SINC(11)=’1’ and R_SINC(15 downto 11)/="00001" then
SY_P_LO:=(DY-1) shl 11;
elsif R_SINC(12)=’1’ and R_SINC(15 downto 12)/="0001" then
SY_P_LO:=(DY-1) shl 12;
elsif R_SINC(13)=’1’ and R_SINC(15 downto 13)/="001" then
SY_P_LO:=(DY-1) shl 13;
elsif R_SINC(14)=’1’ and R_SINC(15 downto 14)/="01" then
SY_P_LO:=(DY-1) shl 14;
else
SY_P_LO:=0;
end if;
SY_P:=SY_P_LO + SY_P_HI;
Abbildung 109: Speedchart-Diagramm TIM/GR CPU/SY SPLIT
Anhang D.2
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