DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Abbildung 105: Speedchart-Diagramm TIM/GR CPU/GP CMD/CLIP
CLIP
entry
T1
S1
T4 #1
A: -- clip coordinates if necessary
-- set WINT:=1 if coord’s were clipped
if YS_viol=’1’ then
R_DADR(31 downto 16):=R_WSTARTY;
-- clip Y start
if YE_viol=’1’ then
R_DY:=(WENDY-WSTARTY+1) mod 65536;
-- two side clip, new area height
else
R_DY:=(DY+DYADR-WSTARTY) mod 65536;
-- Y start clip, adapt DY
end if;
WINT_RQ:=’1’; -- interrupt: wind. viol.
elsif YE_viol=’1’ then
R_DY:=(WENDY-DYADR) mod 65536;
-- clip Y end only, new area height
WINT_RQ:=’1’; -- interrupt: wind. viol.
end if;
if XS_viol=’1’ then
R_DADR(15 downto 00):=R_WSTARTX;
-- clip X start
if XE_viol=’1’ then
R_DX:=(WENDX-WSTARTX+1) mod 65536;
-- two side clip, new area width
else
R_DX:=(DX+DXADR-WSTARTX) mod 65536;
-- X start clip, adapt DX
end if;
WINT_RQ:=’1’; -- interrupt: wind. viol.
elsif XE_viol=’1’ then
R_DX:=(WENDX-DXADR) mod 65536;
-- clip X end only, new area width
WINT_RQ:=’1’; -- interrupt: wind. viol.
end if;
C: (DXADR > WENDX) or
((DXADR+DX-1) < WSTARTX) or
(DYADR > WENDY) or
((DYADR+DY-1) < WSTARTY)
A: CINT_RQ:=’1’;
-- interrupt: window empty
T5 #0
S2
T2
A: -- convert DXADR/DYADR
-- (X/Y dest. address)
-- to R_DYADR
-- (linear destination pixel address)
R_DADR:=DADR_P;
exit
Subdiag Actions of
A: XS_viol:=’1’ when DXADR < WSTARTX else ’0’;
XE_viol:=’1’ when (DXADR+DX-1) < WENDX else ’0’;
YS_viol:=’1’ when DYADR < WSTARTY else ’0’;
YE_viol:=’1’ when (DYADR+DY-1) < WENDY else ’0’;
Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Anhang D.2
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