DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
RL_MSC
entry
T1
blank
Subdiag Actions of
A: MSCNTV:=MSCNT mod 4096;
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
C: (HCOUNT+1) mod 65536=HSBLNK
-- HCOUNT=HSBLNK-1
A: DISCLK:=’1’;
MSCNT:=0;
T3 #0
T2
C: RELAREA=’1’ and RLE=’1’ and
(HCOUNT+1) mod 65536=HEBLNK
-- HCOUNT=HEBLNK-1
A: DISCLK:=’0’;
MSCNT:=0xFFF;
DISINC:=’1’;
if MSC_SFT=0 then
MSC_itv:=(DISCLK bor VClk_in)
band MSC_reload; -- pulse after reload
else
MSC_itv:=’0’
when ((MSCNT=0xFFE and DISINC=’0’)
or MSC_reload=’0’)
else ’1’;
end if;
clock
case XZ is
when "000" => LD_itv:=DISCLK bor VClk_in;
when "001" => LD_itv:=’0’
when MSCNTV(0)=’1’ else ’1’;
when "010" => LD_itv:=’0’
when MSCNTV(1 downto 0)="11"
else ’1’;
when "011" => LD_itv:=’0’
when MSCNTV(2 downto 0)="111"
else ’1’;
when "100" => LD_itv:=’0’
when MSCNTV(3 downto 0)="1111"
else ’1’;
when "101" => LD_itv:=’0’
when MSCNTV(4 downto 0)="11111"
else ’1’;
when "110" => LD_itv:=’0’
when MSCNTV(5 downto 0)="111111"
else ’1’;
when "111" => LD_itv:=’0’
when MSCNTV(6 downto 0)="1111111"
else ’1’;
end case;
-- test outputs
DISCLK_ot :=DISCLK;
MSC_ot :=MSC_itv;
LD_ot :=LD_itv;
RAS_ot :=RAS_itv;
CAS_ot :=CAS_itv;
MOE_ot :=MOE_itv;
MWE_ot :=MWE_itv;
MSF_ot :=MSF_itv;
RCA_ot :=RCA_itv(8 downto 0);
MSCNT_ot :=MSCNT mod 4096;
TAPCNT_ot :=TAPCNT mod 2048;
ROWCNT_ot :=ROWCNT mod 4096;
CALC_NRL_ot :=CALC_NRL mod 256;
CALC_NRH_ot :=CALC_NRH mod 256;
SMR_req_ot :=SMR_request;
SMR_high_ot :=SMR_high;
-- for VRAM model control:
Clk_Div:=’0’ when MSC_SFT=0
and DISCLK=’0’ -- MSC = VClk
and DISINC=’0’ -- disable 1st pulse
else ’1’;
T4 #1
Abbildung 65: Speedchart-Diagramm VIDEO/RELOAD/RL MSC
Anhang C.2
Seite 98
A: case MSC_SFT is
when 0 => MSCNT:=0xFFF;
when 1 => MSCNT:=((MSCNT + 1) mod 2) + 0xFFE;
when 2 => MSCNT:=((MSCNT + 1) mod 4) + 0xFFC;
when 3 => MSCNT:=((MSCNT + 1) mod 8) + 0xFF8;
when 4 => MSCNT:=((MSCNT + 1) mod 16) + 0xFF0;
when 5 => MSCNT:=((MSCNT + 1) mod 32) + 0xFE0;
when 6 => MSCNT:=((MSCNT + 1) mod 64) + 0xFC0;
when 7 => MSCNT:=((MSCNT + 1) mod 128) + 0xF80;
when 8 => MSCNT:=((MSCNT + 1) mod 256) + 0xF00;
when 9 => MSCNT:=((MSCNT + 1) mod 512) + 0xE00;
when 10 => MSCNT:=((MSCNT + 1) mod 1024) + 0xC00;
when 11 => MSCNT:=((MSCNT + 1) mod 2048) + 0x800;
when others => MSCNT:=(MSCNT + 1) mod 4096;
end case;
if MSCNT=0xFFF and DISINC=’0’ then
TAPCNT:=TAPCNT + 1 when TAPCNT/=0x7FF
else 0x000 when SRL="11" -- 2048-2048
else 0x400 when SRL="10" -- 2048-1024
else 0x600 when SRL="01" -- 2048-512
else 0x700; -- 2048-256
end if;
if MSCNT=0xFFF and DISINC=’0’ and CALC_NRH/=0
and TAPCNT=0x7FF then
SMR_request:=’1’;
SMR_high:=’1’; -- high half SR data just finished
end if;
if MSCNT=0xFFF and DISINC=’0’ and CALC_NRL/=0
and ((SRL="00" and TAPCNT=0x77F)
or (SRL="01" and TAPCNT=0x6FF)
or (SRL="10" and TAPCNT=0x5FF)
or (SRL="11" and TAPCNT=0x3FF)) then
SMR_request:=’1’;
SMR_high:=’0’; -- low half SR data just finished
end if;
DISINC:=’0’;