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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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Chapter 7<br />

SYSTEMATIC EMBEDDED SOFTWARE<br />

GENERATION FROM SYSTEMC<br />

F. Herrera, H. Posadas, P. Sánchez and E. Villar<br />

TEISA Dept., E.T.S.I. Industriales y Telecom., University of Cantabria, Avda. Los Castros s/n,<br />

39005 Santan<strong>de</strong>r, Spain; E-mail: {fherrera, posadash, sanchez, villar}@teisa.unican.es<br />

Abstract. The embed<strong>de</strong>d software <strong>de</strong>sign cost represents an important percentage of the<br />

embed<strong>de</strong>d-system <strong>de</strong>velopment costs [1]. This paper presents a method <strong>for</strong> systematic embed<strong>de</strong>d<br />

software generation that reduces the software generation cost in a plat<strong>for</strong>m-based HW/SW<br />

co<strong>de</strong>sign methodology <strong>for</strong> embed<strong>de</strong>d systems based on SystemC. The goal is that the same<br />

SystemC co<strong>de</strong> allows system-level specification and verification, and, after SW/HW partition,<br />

SW/HW co-simulation and embed<strong>de</strong>d software generation. The C++ co<strong>de</strong> <strong>for</strong> the SW partition<br />

(processes and process communication including HW/SW interfaces) is systematically generated<br />

including the user-selected embed<strong>de</strong>d OS (e.g.: the eCos open source OS).<br />

Key words: <strong>Embed<strong>de</strong>d</strong> <strong>Software</strong> generation, SystemC, system-level <strong>de</strong>sign, plat<strong>for</strong>m based<br />

<strong>de</strong>sign<br />

1. INTRODUCTION<br />

The evolution of technological processes maintains its exponential growth;<br />

810 Mtrans/chip in 2003 will become 2041 Mtrans/chip in 2007. This obliges<br />

an increase in the <strong>de</strong>signer productivity, from 2.6 Mtrans/py in 2004 to 5.9<br />

Mtrans/py in 2007, that is, a productivity increase of 236% in three years<br />

[2]. Most of these new products will be embed<strong>de</strong>d System-on-Chip (<strong>SoC</strong>)<br />

[3] and inclu<strong>de</strong> embed<strong>de</strong>d software. In fact, embed<strong>de</strong>d software now routinely<br />

accounts <strong>for</strong> 80% of embed<strong>de</strong>d system <strong>de</strong>velopment costs [1].<br />

Today, most embed<strong>de</strong>d systems are <strong>de</strong>signed from a RT level <strong>de</strong>scription<br />

<strong>for</strong> the HW part and the embed<strong>de</strong>d software co<strong>de</strong> separately. Using a classical<br />

top-down methodology (synthesis and compilation) the implementation is<br />

obtained. The 2001 International Technology Roadmap <strong>for</strong> Semiconductors<br />

(ITRS) predicts the substitution (during the coming years) of that waterfall<br />

methodology by an integrated framework where co<strong>de</strong>sign, logical, physical<br />

and analysis tools operate together. The <strong>de</strong>sign step being where the <strong>de</strong>signer<br />

envisages the whole set of inten<strong>de</strong>d characteristics of the system to be<br />

implemented, system-level specification acquires a key importance in this new<br />

This work has been partially supported by the Spanish MCYT through the TIC-2002-00660<br />

project.<br />

83<br />

A Jerraya et al. (eds.), <strong>Embed<strong>de</strong>d</strong> <strong>Software</strong> <strong>for</strong> SOC, 83–93, 2003.<br />

© 2003 Kluwer Aca<strong>de</strong>mic Publishers. Printed in the Netherlands.

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