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SDRAM-Energy-Aware Memory Allocation 327 dynamic energy. At the same time, the static energy consumption slightly reduces since less misses results in a shorter execution time (see the static energy of the example in Figure 24-2 executed at 600 MHz.). However, when extra banks do not significantly reduce the page-miss rate anymore, the dynamic energy savings become smaller than the extra static energy needed to keep the banks in CS/STBY-mode. The total energy consumption increases then again. A nice illustration of this is Quick24to8 in Table 24-5. The total energy consumption decreases up to three banks and then increases again due to the extra static energy. Also, in Figure 24-2. the total energy consumption increases again when more than five banks are used. From these examples, we see that an optimal number of active banks exist. The optimal number of banks depends on the ratio of static versus dynamic energy. When the banks become more active (e.g. because more tasks are activated or the processor frequency is increased), the dynamic energy becomes more important than the static energy and the optimal number of Please check no. of figures and no. of tables Table 24-5. Energy comparison of several allocation strategies. Tasks (100 Mhz) Nds 1 2 3 4 5 6 Fir+Conv(SA) Fir+Conv(MA) Fir+Conv(RA) Fir+Conv(GP) Fir+Conv(BE) R2Y+Cmp(SA) R2Y+Cmp(MA) R2Y+Cmp(RA) R2Y+Cmp(GP) R2Y+Cmp(BE) R2Y+Cmp+Conv(SA) R2Y+Cmp+Conv(MA) R2Y+Cmp+Conv(RA) R2Y+Cmp+Conv(GP) R2Y+Cmp+Conv(BE) R2Y+Cmp+Conv+Dct(SA) R2Y+Cmp+Conv+Dct(MA) R2Y+Cmp+Conv+Dct(RA) R2Y+Cmp+Conv+Dct(GP) R2Y+Cmp+Conv+Dct(BE) Fir+Conv(SA) Fir+Conv(MA) Fir+Conv(RA) Fir+Conv(GP) Fir+Conv(BE) 7 7 7 7 7 8 8 8 8 8 12 12 12 12 12 18 18 18 18 7 7 7 7 7 _ 20958 20958 – 20958 – 4986 4986 – 4986 – 23531 23531 – 23531 – 26195 26195 – 26195 — 20480 20480 – 20480 20993 9858 15712 20993 10250 4859 3832 4362 4859 4041 – 13872 13872 – 13769 – 16684 21896 – 16212 20305 9261 14938 20305 9526 20993 9269 13834 9943 9269 4859 1877 3733 3821 2031 24082 12456 12456 24082 13468 – 15165 19332 – 16143 20305 7582 11664 8395 8219 20993 8641 12381 8641 9515 4859 1521 3407 1521 1553 24082 11392 11392 13034 11515 26647 13665 17947 26647 14224 20305 6600 11421 7842 7623 20993 8641 12436 8641 8942 4859 1521 3368 1521 1821 24082 10109 10109 11987 9907 26647 13132 17517 15598 13405 20305 6494 10115 6494 6494 20993 8641 10990 8641 8964 4859 1521 3209 1521 2089 24082 10060 10060 9695 10206 26647 12514 17696 14551 12758 20305 6473 9196 6473 6473
328 Chapter 24 banks increases. E.g. in Figure 24-2. the optimal number of banks increases from five to six when the processor frequency changes from 100 MHz to 600 MHz. SA performs poorly when the energy consumption is dominated by the dynamic energy. It cannot exploit idle banks owned by other processors to reduce the number of page-misses. The difference between SA and MA (an approximation of the best-possible assignment) is large (more than 300), indicating that sharing SDRAM memories is an interesting option for heterogeneous multi-processor platforms. It increases the exploration space such that better assignments can be found. When the banks are not too heavily used, even no performance penalty is present (see below). We also observe in Figure 24-2. that existing commercial multi-processor memory allocators (RA) perform badly compared to MA. This suggests that large headroom for improvement exists. When only one bank is available, obviously all memory allocation algorithms produce the same results. With an increasing number of banks the gap between RA and MA first widens as a result of the larger assignment freedom (up to 55% for Rgb2Yuv and Cmp with four banks). However, the performance of the RA improves with an increasing number of banks: the chances increase that RA distributes the data structures across the banks, which significantly reduces the energy consumption. Therefore, when the number of banks becomes large the gap between RA and MA becomes smaller again (50% for Rgb2Yuv and Cmp with six banks). For higher processor frequencies the static energy consumption decreases and the potential gains become larger. E.g. for Convolve and Cmp the gap increases from 26% to 34%. Figure 24-2 shows how BE outperforms RA. Results in Table 24-6. suggest an improvement up to 50% (see Rgb2Yuv and Cmp with four banks). Moreover, BE often comes close to the MA results. The difference between BE and MA is always less than 23%. When the number of tasks in the application becomes large (see task-set in Table 24-6. which consists of 10 tasks), we note a small energy loss of BE compared to RA for the first taskset and eight banks are used. In this case 50 data structures are allocated in Table 24-6. Energy comparison of several allocation strategies. Tasks(l00Mhz) Nds Nbank(uJ) 8 16 32 2Quick+2R2Y+2Rin+Cmp+2Lzw(SA) 2Quick+2R2Y+2Rin+Cmp+2Lzw(RA) 2Quick+2R2Y+2Rin+Cmp+2Lzw(MA) 2Quick+2R2Y+2Rin+Cmp+2Lzw(GP) 2Quick+2R2Y+2Rin+Cmp+2Lzw(BE) 2Quick+2R2Y+2Rin+Cmp+2Lzw(Estatic) 50 50 50 50 50 50 _ 49525 47437 – 51215 10227 48788 41872 37963 38856 40783 9045 48788 45158 41610 34236 35371 8489
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Chapter 16 EMBEDDED SW IN DIGITAL A
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Embedded SW in Digital AM-FM Chipse
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Embedded SW in Digital AM-FM Chipse
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PART V: SOFTWARE OPTIMISATION FOR E
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Chapter 17 CONTROL FLOW DRIVEN SPLI
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Control Flow Driven Splitting of Lo
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Chapter 18 DATA SPACE ORIENTED SCHE
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Data Space Oriented Scheduling 233
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Chapter 19 COMPILER-DIRECTED ILP EX
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Compiler-Directed ILP Extraction 24
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Chapter 20 STATE SPACE COMPRESSION
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State Space Compression in History
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Chapter 21 SIMULATION TRACE VERIFIC
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Chapter 29 HARDWARE/SOFTWARE TECHNI
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HW/SW are Techniques for Improving
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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