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Hardware and Software Partitioning of Operating Systems 189 desired RTOS features most suitable for the user’s needs [8–10]. Some RTOS features have both hardware and software versions available. Figure 15-2 is a snapshot of the “GUI tool” shown in the center of Figure 15-3. 3.1. Methodology Figure 15-3 shows a novel approach to automating the partitioning of a hardware/software RTOS between a few pre-designed partitions. The hardware/software RTOS generation framework takes as input the following four items: Hardware RTOS Library This hardware RTOS library currently consists of SoCLC, SoCDDU and SoCDMMU [11–16]. Base System Library The base system library consists of basic elements such as bus arbiters and memory elements such as various caches (L1, L2, etc.). Furthermore,
190 Chapter 15 we also need in the base system library I/O pin descriptions of all processors supported in our system. Software RTOS Library In our case, the software RTOS library consists of Atalanta [17]. User Input Currently the user can select number of processors, type of each processor (e.g., PowerPC 750 or ARM9TDMI), deadlock detection in hardware (SoCDDU) or software, dynamic memory management in hardware (SoCDMMU) or software, a lock cache in hardware (SoCLC), and different Inter-Procedure Call (IPC) methods. (Note that while all the IPC methods are partly implemented in software, the IPC methods might also depend on hardware support – specifically, if SoCLC is chosen, then lock variables will be memory mapped to the SoCLC.) The three files on the right-hand-side of Figure 15-3 (the Makefile, User.h and Verilog files) show the configuration files output to glue together the hardware/software RTOS Intellectual Property (IP) library components chosen in the multiprocessor SoC specified by the user. 3.2. Target SoC The target system for the Framework is an SoC consisting of custom logic, reconfigurable logic and multiple PEs sharing a common memory, as shown in Figure 15-1. Note that all of the hardware RTOS components (SoCDMMU, SoCLC and SoCDDU) have well-defined interfaces to which any PE – including a hardware PE (i.e., a non Von-Neumann or non-instruc-tion-set processing element) – can connect and thus use the hardware RTOS component’s features. In other words, both the custom logic and reconfig-urable logic can contain specialized PEs which interface to the hardware RTOS components.
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Page 172 and 173: Chapter 12 INTERACTIVE RAY TRACING
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Page 188 and 189: Porting a Network Cryptographic Ser
Page 198 and 199: PART IV: EMBEDDED OPERATING SYSTEMS
Page 200 and 201: Chapter 14 INTRODUCTION TO HARDWARE
Page 202 and 203: Introduction to Hardware Abstractio
Page 208 and 209: Chapter 15 HARDWARE/SOFTWARE PARTIT
Page 212 and 213: Hardware and Software Partitioning
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Page 234 and 235: PART V: SOFTWARE OPTIMISATION FOR E
Page 236 and 237: Chapter 17 CONTROL FLOW DRIVEN SPLI
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Data Space Oriented Scheduling 239
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Chapter 19 COMPILER-DIRECTED ILP EX
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Compiler-Directed ILP Extraction 24
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Chapter 20 STATE SPACE COMPRESSION
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State Space Compression in History
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Chapter 21 SIMULATION TRACE VERIFIC
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Simulation Trace Verification for Q
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PART VI: ENERGY AWARE SOFTWARE TECH
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Chapter 22 EFFICIENT POWER/PERFORMA
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Efficient Power/Performance Analysi
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Chapter 23 DYNAMIC PARALLELIZATION
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Dynamic Parallelization of Array 30
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Chapter 24 SDRAM-ENERGY-AWARE MEMOR
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SDRAM-Energy-Aware Memory Allocatio
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PART VII: SAFE AUTOMOTIVE SOFTWARE
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Chapter 25 SAFE AUTOMOTIVE SOFTWARE
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Safe Automotive Software Developmen
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PART VIII: EMBEDDED SYSTEM ARCHITEC
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Chapter 26 EXPLORING HIGH BANDWIDTH
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Exploring High Bandwidth Pipelined
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Chapter 27 ENHANCING SPEEDUP IN NET
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Enhancing Speedup in Network Proces
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Chapter 28 ON-CHIP STOCHASTIC COMMU
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On-Chip Stochastic Communication 37
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Chapter 29 HARDWARE/SOFTWARE TECHNI
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HW/SW are Techniques for Improving
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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