Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

212 Chapter 16
done (at least few seconds). Based upon the current figures, 3 seconds of
simulation (synchronisation and preliminary receiving phase) will take approximately
40 days (assumption: 1 Million instruction per hour). This validation
will be the next step of our design.
5. CONCLUSIONS
The methodology applied during this HW/SW co-design allows us to cover
efficiently the platform requirements. Several remaining points are still open
and will be validated during the integration phase directly on the physical
platform (mainly the OS, scheduler and real-time issue). However, all the open
points are related to the SW and do not impact the HW definition of the
platform.
Nevertheless new solution has to be built to allow complete validation of
SoC including HW modules and all the SW layer including scheduler and
operating system.