Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Compiler-Directed ILP Extraction 249
and equals 2 for operation a. Assuming that
the probability of scheduling an operation at any time step in its time frame
is given by a uniform distribution [22], the contribution to the load of an
operation op at time step t in its time frame is given by In Figure
19-1, the contributions to the load of all the addition operations (labeled a,
c, d, f, g and h) are indicated by the shaded region to the right of the
operations. To obtain the total load for type fu at a time step t, we sum the
contribution to the load of all operations that are executable on resource type
fu at time step t. In Figure 19-1, the resulting total adder load profile is shown.
The thick vertical line in the load profile plot is an indicator of the capacity
of the machine’s datapath to execute instructions at a particular time step. (In
the example, we assume a datapath that contains 2 adders.) Accordingly, in
step 1 of the load profile, the shaded region to the right of the thick vertical
line represents an over-subscription of the adder datapath resource. This
indicates that, in the actual VLIW code/schedule, one of the addition operations
(i.e. either operation a, d or g) will need to be delayed to a later time
step.
2.2. Load balancing through speculation
We argue that, in the context of VLIW/EPIC machines, the goal of compiler
transformations aimed at speculating operations should be to “redistribute/
balance” the load profile of the original/input kernel so as to enable a more
effective utilization of the resources available in the datapath. More specifically,
the goal should be to judiciously modify the scheduling ranges of the
kernel’s operations, via speculation, such that overall resource contention is
decreased/minimized, and consequently, code performance improved. We
illustrate this key point using the example CDFG in Figure 2(a), and assuming
a datapath with 2 adders, 2 multipliers and 1 comparator. Figure 19-2(b) shows
the adder load profile for the original kernel while Figure 19-3(a) and Figure
19-3(b) show the load profiles for the resulting CDFG’s with one and three