Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Evaluation of Applying SpecC to the Integrated Design Method 149
DMA circuit is realized by using intellectual property (IP). However, there
are systems where the device cannot be the bus master or it cannot access a
part of memory used by the processor. In these kinds of systems the DMA
cannot be realized.
Since the partition point is changed, the byte channel is converted into a
hardware. The channel conversion rule to the hardware is described in [7].
6.3. Conversion result and discussion
Figure 11-6 shows the relation between the transmitter part of SIO system in
SpecC and the software and hardware obtained from the above conversion.
The implementation behaves correctly on the prototype system. The hardware
part with the receiver uses 951 cells in FPGA and a maximum frequency of
40 MHz.
By using a DMA circuit, changing the partition point of the SIO system
into a PPP packet channel is possible. The results show that the number of
cells in the FPGA implementation of the conversion with PPP packet channel
is 3 times that of the conversion with the byte channel. This is because a DMA
is included and the functions realized as hardware increased. Furthermore,
since the interface converted from PPP packet channel delivers 32 bit data
while the interface converted from the byte channel delivers only 8 bit data,
the data size handled in the glue logics increased 4 times compared with the
previous conversion. In this conversion, the behavior and the channel are
converted to hardware module one to one. However, the behavior and the
channel can be merged into one module for optimization.
One problem of realizing the hardware using DMA is that the head address
of the structure may vary when it is accessed from the processor or from the
device. This is because the connections of the memory, the processor and the
DMA circuit vary or the processor performs a memory translation. This
problem can be solved by translating the address passed by the software to
the addressed seen by the device.
7. CONCLUSION
In this paper, we have presented an integrated design method of a device and
a device driver and we have evaluated the applicability of SpecC to the
proposed method using the SIO system.
Evaluations have shown that the SIO system can be mechanically converted
by following the description guidelines and preparing a library for channels.
Since the SIO system can be described using parallelism, synchronization and
communication statements in SpecC, we have verified that SpecC can be used
as the description language for the proposed integrated design method of a
device driver and a device.
Furthermore, we have verified that the conversion by changing the parti-