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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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State Space Compression in History 263<br />

The communication through ports occurs by means of unidirectional, pointto-point<br />

channels.<br />

One of the main steps of our software synthesis methodology is the generation<br />

of a task schedule, verifying that (1) it is a cyclic schedule, (2) it has<br />

no <strong>de</strong>adlocks and (3) the schedule requires boun<strong>de</strong>d memory resources (in<br />

other words, the cyclic execution of the program makes use of a finite number<br />

of buffers). The system is specified in a high level language similar to C but<br />

modified to allow communication operations. Processes are <strong>de</strong>scribed as<br />

sequential programs that are executed concurrently. Later this specification<br />

is compiled to its un<strong>de</strong>rlying Petri net mo<strong>de</strong>l. The scheduling process is carried<br />

out by means of reachability analysis <strong>for</strong> that Petri net [2, 7].<br />

Traditionally, each of the processes of the system specification will be<br />

separately compiled on the target architecture. On the contrary, our synthesis<br />

process builds a set of tasks from the functional processes that are present in<br />

the starting specification. Each task is associated to one uncontrollable input<br />

port and per<strong>for</strong>ms the operations required to react to an event of that port. The<br />

novel i<strong>de</strong>a is that those tasks may differ from the user specified processes.<br />

The compiler trans<strong>for</strong>mations are applied on each of these tasks, there<strong>for</strong>e<br />

optimizing the co<strong>de</strong> that must be executed in response to an external event.<br />

Figure 20-1. A sketches this i<strong>de</strong>a. It <strong>de</strong>picts two processes A and B, each<br />

of them reading data from its corresponding ports. Processes communicate<br />

by means of the channel C.<br />

However, the data that process B reads from port is processed in<strong>de</strong>pen<strong>de</strong>ntly<br />

of the data read from channel C. Hence, an efficient scheduling<br />

algorithm could reor<strong>de</strong>r the source co<strong>de</strong> to construct the threads 1 and 2<br />

<strong>de</strong>picted in Figure 20-1.B. In this way, architecture specific optimizations will<br />

be per<strong>for</strong>med on these separate co<strong>de</strong> segments or tasks.<br />

Next sections introduce the fundamentals of the scheduling approach used<br />

in our software synthesis methodology.

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