Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

202 Chapter 15
tion (RTOS5) are available in references [9] and [16]. In this section, we will
focus our attention on a comparison of the first configuration (RTOS1), the
third configuration (RTOS3) and the last configuration (RTOS6).
To compare RTOS1, RTOS3 and RTOS6, we decided to use the database
example described in Example 5-2. The base architecture for all three systems
is the same: three MPC755 processors connected via a single bus to 16 MB
of L2 memory and to reconfigurable logic. This architecture can be seen in
Figure 15-13 with the RTU instantiated in the reconfigurable logic. Each
MPC755 has separate instruction and data caches each of size 32 KB. Our
first system configuration of Figure 15-13 uses RTOS1; therefore, with a
pure software RTOS, synchronization is performed with software semaphores
and spin-locks in the system. Note that in this first system, all of the reconfigurable
logic is available for other uses as needed. The second system uses
RTOS3 and thus instantiates an SoCLC in the reconfigurable logic block of
Figure 15-13. Finally, as shown in Figure 15-13, our third system includes the
RTU (see Figure 15-10 in Section 5), exploiting the reconfigurable logic for
scheduling, synchronization and even time-related services. In short, the
hardware RTU in Figure 15-13 handles most of the RTOS services.
Simulations of two database examples were carried out on each of these
three systems using Seamless CVE [15], as illustrated on the far right-hand
side of Figure 15-9. We used Modelsim from Mentor Graphics for mixed
VHDL/Verilog simulation and XRAY debugger from Mentor Graphics for
application code debugging. To simulate each configured system, both the
software part including application and the hardware part of the Verilog top
module were compiled. Then the executable application and the multiprocessor
hardware setup consisting of three MPC755’s were connected in
Seamless CVE.
Experimental results in Table 15-1 present the total execution time of (i)
simulation with software semaphores, (ii) simulation with SoCLC (hardwaresupported
semaphores) and (iii) simulation with RTU. As seen in the table,