Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Chapter 10
SCHEDULING AND TIMING ANALYSIS OF
HW/SW ON-CHIP COMMUNICATION IN
MP SOC DESIGN
Youngchul Cho1, Ganghee Lee1, Kiyoung Choi1, Sungjoo Yoo 2 and
Nacer-Eddine Zergainoh 2
1 Seoul National University, Seoul, Korea; 2 TIMA Laboratory, Grenoble, France
Abstract. On-chip communication design includes designing software parts (operating system,
device drivers, interrupt service routines, etc.) as well as hardware parts (on-chip communication
network, commign space, we need fast scheduling and timing analysis. In this work, we
tackle two problemunication interfaces of processor/IP/memory, etc.). For an efficient
exploration of its dess. One is to incorporate the dynamic behavior of software (interrupt
processing and context switching) into on-chip communication scheduling. The other is to reduce
on-chip data storage required for on-chip communication, by making different communications
to share a physical communication buffer. To solve the problems, we present both integer linear
programming formulation and heuristic algorithm.
Key words: MP SoC, on-chip communication, design space exploration, communication
scheduling
1. INTRODUCTION
In multiprocessor system on chip (MP-SoC) design, on-chip communication
design is one of crucial design steps. By on-chip communication design, we
mean (1) mapping and scheduling of on-chip communications and (2) the
design of both the hardware (HW) part of communication architecture (communication
network, communication interfaces, etc.) and the software (SW)
part (operating system, device drivers, interrupt service routines (ISRs), etc.).
We call the two parts HW communication architecture and SW communication
architecture, respectively.
In our work, we tackle two problems (one for SW and the other for HW)
in on-chip communication design. First, we present a method of incorporating,
into on-chip communication scheduling, the dynamic behavior of SW (interrupt
processing and context switching) related to on-chip communication.
Second, to reduce on-chip data storage (in our terms, physical communication
buffer) required for on-chip communication, we tackle the problem of
making different communications to share a physical communication buffer
in on-chip communication scheduling.
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A Jerraya et al. (eds.), Embedded Software for SOC, 125–136, 2003.
© 2003 Kluwer Academic Publishers. Printed in the Netherlands.