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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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Chapter 22<br />

EFFICIENT POWER/PERFORMANCE<br />

ANALYSIS OF EMBEDDED AND GENERAL<br />

PURPOSE SOFTWARE APPLICATIONS<br />

A Pre-Characterization Free Approach<br />

Venkata Syam P. Rapaka‚ and Diana Marculescu<br />

Carnegie Mellon University<br />

Abstract. This chapter presents a novel approach <strong>for</strong> an efficient‚ yet accurate estimation<br />

technique <strong>for</strong> power consumption and per<strong>for</strong>mance of embed<strong>de</strong>d and general-purpose<br />

applications. Our approach is adaptive in nature and is based on <strong>de</strong>tecting sections of co<strong>de</strong><br />

characterized by high temporal locality (also called hotspots) in the execution profile of the<br />

benchmark being executed on a target processor. The technique itself is architecture and input<br />

in<strong>de</strong>pen<strong>de</strong>nt and can be used <strong>for</strong> both embed<strong>de</strong>d‚ as well as <strong>for</strong> general-purpose processors. We<br />

have implemented a hybrid simulation engine‚ which can significantly shorten the simulation<br />

time by using on-the-fly profiling <strong>for</strong> critical sections of the co<strong>de</strong> and by reusing this in<strong>for</strong>mation<br />

during power/per<strong>for</strong>mance estimation <strong>for</strong> the rest of the co<strong>de</strong>. By using this strategy‚ we<br />

were able to achieve up to 20× better accuracy compared to a flat‚ non-adaptive sampling scheme<br />

and a simulation speed-up of up to 11.84× with a maximum error of 1.03% <strong>for</strong> per<strong>for</strong>mance<br />

and 1.92% <strong>for</strong> total energy on a wi<strong>de</strong> variety of media and general-purpose applications.<br />

Key words: power estimation‚ simulation speedup‚ application hotspots<br />

1.<br />

INTRODUCTION<br />

<strong>Embed<strong>de</strong>d</strong> or portable computer systems play an increasingly important role<br />

in today’s quest <strong>for</strong> achieving true ubiquitous computing. Since power<br />

consumption and per<strong>for</strong>mance have a direct impact on the success of not only<br />

embed<strong>de</strong>d‚ but also high per<strong>for</strong>mance processors‚ <strong>de</strong>signers need efficient and<br />

accurate tools to evaluate the efficacy of their software and architectural<br />

innovations.<br />

To estimate power consumption and per<strong>for</strong>mance‚ a <strong>de</strong>signer can make a<br />

choice from a variety of simulators at various levels of abstraction‚ ranging<br />

from transistor or layout-level [1] to architectural [2‚ 3] and instruction-level<br />

[4–7]. The lowest level simulators provi<strong>de</strong> the most <strong>de</strong>tailed and accurate<br />

statistics‚ while the higher-level simulators tra<strong>de</strong> off accuracy <strong>for</strong> simulation<br />

speed and portability. Although high-level simulators offer high speedup when<br />

compared to low-level simulators‚ they are still time consuming and may<br />

take days to simulate very large‚ practical benchmarks. At the same time‚<br />

289<br />

A Jerraya et al. (eds.)‚ <strong>Embed<strong>de</strong>d</strong> <strong>Software</strong> <strong>for</strong> SOC‚ 289–300‚ 2003.<br />

© 2003 Kluwer Aca<strong>de</strong>mic Publishers. Printed in the Netherlands.

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