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Exploring High Bandwidth Pipelined Cache Architecture 353 to data output delay (MDD). Figure 26-5 shows the variation of these delays with banking for different technology generations. The delay for a particular technology is normalized with respect to the clock cycle time for that
354 Chapter 26 technology as given in Figure 26-4. To account for latch overhead, latch setup time and propagation delay are added to the WD + BSD and MDD. This overhead is around 10% of the clock cycle time for a given technology. DD remains within the bound of one clock cycle irrespective of technology scaling. Since Ndwl is kept constant, banking the cache does not affect DD. WD + BSD does not scale well with technology. Scaling down the technology requires more clock cycles for a given bank configuration. For example, the number of cycles required for 4 × 2 bank configuration is one for and technology, whereas for and it is two cycles, and for technology it is three cycles (Figure 26-4). More banking makes the bit-line delay to go down. The goal behind banking is to get an optimal configuration for which the word-line driver to sense amplifier delay (with latch overhead) is equal a single CPU cycle. Overbanking will increase energy and area overhead without any performance improvement. Figure 26-5(b) shows that for a technology, the bit-line delay remains within the limit of one cycle for all bank configurations. Scaling the technology requires more banking to achieve one cycle bit-line delay, e.g. for optimal banking is 8 × 2. Similarly for and technologies, optimal banking configurations are 16 × 2, 32 × 2, and 64 × 2, respectively. For optimal banking, WD + BSD can be confined to a single clock cycle; however, it increases MDD. Since MDD consists of wire delay due to routing of the banks, it also does not scale effectively with technology. In the proposed scheme, the MDD is determined by the optimal banking configuration for a bit-line delay. Analyzing MDD (Figure 26-5(c)) for the optimal configurations shows that for and technology, MDD remains within one clock cycle. For and technologies, optimal bank configurations, decided by bit-line delay, are 32 × 2 and 64 × 2 respectively, for which required MDD goes beyond one clock cycle. To make the cache fully pipelined with access frequency equivalent to clock frequency, the multiplexer can be divided into multiple pipeline stages. Table 26-2 shows the optimal banking requirement and the number of pipeline stages required to make the cache fully pipelined with access frequency of one clock cycle. The design technique has its own disadvantages of having extra energy and area overhead. Table 26-3 shows the area and energy overhead associated with Table 26-2. Number of cache pipeline stages. Technology Banks (Ndbl × Ndwl) Decoder stage WL-sense amp stage Mux to dataout stages Total cache pipeline stages 0.18 0.13 0.10 0.07 8 × 2 16 × 2 32 × 2 64 × 2 1 1 1 1 1 1 1 1 1 2 2 2 3 3 4 4
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Chapter 16 EMBEDDED SW IN DIGITAL A
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Embedded SW in Digital AM-FM Chipse
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Embedded SW in Digital AM-FM Chipse
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PART V: SOFTWARE OPTIMISATION FOR E
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Chapter 17 CONTROL FLOW DRIVEN SPLI
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Control Flow Driven Splitting of Lo
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Chapter 18 DATA SPACE ORIENTED SCHE
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Data Space Oriented Scheduling 233
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Chapter 19 COMPILER-DIRECTED ILP EX
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Compiler-Directed ILP Extraction 24
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Chapter 20 STATE SPACE COMPRESSION
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State Space Compression in History
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Chapter 21 SIMULATION TRACE VERIFIC
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Simulation Trace Verification for Q
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PART VI: ENERGY AWARE SOFTWARE TECH
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Chapter 22 EFFICIENT POWER/PERFORMA
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Efficient Power/Performance Analysi
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Page 366 and 367: Chapter 26 EXPLORING HIGH BANDWIDTH
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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Embedded Software for SoC - Grupo de MecatrÃ´nica EESC/USP

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