Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

370 Chapter 27
improve IR thereby reducing the RoB occupancy even more. Flow based reuse
reduces the occupancy of the RoB by 1.5% to 3% over the base reuse scheme.
4. CONCLUSIONS
In this article we examined instruction reuse of integer ALU and load instructions
in packet processing applications. To further enhance the utility of reuse
by reducing interference, a flow aggregation scheme that exploits packet correlation
and uses multiple RB’s is proposed. The results indicate that
exploiting instruction reuse with flow aggregation does significantly improve
the performance of our NPU model (24% improvement in speedup in the
best case). IR and speedup that can be achieved depends on the nature of the
network traffic and working set sizes. A direct relationship between reuse and
speedup does not exist. This means that although instruction reuse improves
due to flow aggregation, speedup may not improve proportionally. This is
because speedup depends on a lot of other parameters such as the criticality
of the instruction being reused. Future work would be to simulate the architecture
proposed, evaluate energy issues and determine which instructions
really need to be present in the RB. Interference in the RB can be reduced if
critical instructions are identified and placed in the RB. Further, a detailed
exploration of various mapping schemes is necessary to evenly distribute
related data among RB’s. Finally, we believe that additional reuse can be
recovered from payload processing applications if realistic (non-anonymized)
traffic is used and operand indexing is exploited.
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