Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Energy-Aware Parameter Passing 509
is reached, the actual parameter has already been computed; so, b5 can just
use the value.
The second method, called path control, is based on the idea of using a
variable (or a set of variables) to determine at runtime which path is being
executed. For example, assume that we use a variable p to determine which
path (leading to b5) is being executed. Without loss of generality, we can
assume that if path I is taken p is assigned 1, otherwise p is set to zero. Under
this method, when b5 is reached, we can check the value of p, and depending
on its value, we perform actual parameter value evaluation or not. It should
be noted that, as compared to the first method, this method results in a smaller
executable size (in general); but, it might lead to a higher execution time due
to comparison operation.
4. EXPERIMENTAL RESULTS
To test the effectiveness of our on-demand parameter-passing in reducing
energy consumption, we conducted experiments with five real-life applications
from different application domains: Atr(network address translation),
SP(all-nodes shortest path algorithm), Encr(digital signature for security),
Wood(color-based surface inspection method), and Usonic (feature-based
estimation algorithm).
To evaluate the benefits due to on-demand parameter-passing, we modified
SUIF [2] to implement different parameter-passing strategies. Our on-demand
parameter-passing strategy took less than 1200 lines of C++ code to implement.
We then modified the Shade tool-set to collect data about the
performance and energy behavior of applications. Shade is an execution-driven
ISA (instruction set architecture) and cache memory simulator for Sparc
architectures. We simulated an architecture composed of a Sparc-IIep based
core processor (100 MHz), data (8 KB, 2-way) and instruction (16 KB,
2-way) caches, and a banked memory architecture (using SRAM banks). The
simulator outputs the energy consumptions (dynamic energy only) in these
components and overall application execution time. In particular, it simulates
the parameter-passing activity in detail to collect data for comparing different
parameter-passing strategies. For computing the energy expended in caches
and SRAM banks, the model given by Kamble and Ghose [4] is used. The
energy consumed in the processor core is estimated by counting the number
of instructions of each type and multiplying the count by the base energy
consumption of the corresponding instruction. The base energy consumption
of different instruction types is obtained using a customized version of the
simulator presented in [6]. All energy numbers have been computed for 0.10
micron, 1 V technology.
Figure 36-4 and Figure 36-5 show the percentage improvements in energy
consumption and execution cycles, respectively, when different on-demand