Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Analysis of HW/SW On-Chip Communication in MP SOC Design 133
the timing analysis using the JPEG and IS-95 CDMA examples. Since these
examples require prohibitively long simulation runtime, we exclude simulation.
First we performed experiments with an H.263 video encoder system as
depicted in Figure 10-4(a). It has seven tasks including Source, DCT,
Quantizer (Q), De-Quantizer IDCT, Motion Predictor, and Variable
Length Coder (VLC). Input stream is a sequence of qcif (176 × 144 pixels).
We clustered four tasks (DCT, Q, and IDCT) into a single unit, which
we call Macro Block (MB) Encoder (see Figure 10-4(b)). In the experiment
we used two target architectures: one with point-to-point interconnection
(Figure 10-4(c)) and the other with an on-chip shared bus (Figure 10-4(d)).
In the target architecture, Source and VLC were mapped on ARM7TDMI
microprocessor and MB Encoder and Motion Predictor were mapped on their
own dedicated hardware components. On the ARM7TDMI processor, we ran
an embedded configurable operating system (eCos) [15] of Redhat Inc.
The execution delay of SW for tasks, operating systems, device driver, ISR,
etc. was measured by instruction set simulator (ISS) execution. That of HW
tasks was obtained by VHDL simulator execution. And the software communication
architecture delay is measured by ISS.
Table 10-1 shows the advantage of considering dynamic SW behavior in
the scheduling of task execution and communication. The table presents the
execution cycles of the system obtained by cosimulation, ILP without considering
dynamic SW behavior, ILP with dynamic SW behavior, and heuristic
with dynamic SW behavior, for the two architectures: point-to-point interconnection
and on-chip shared-bus. By considering dynamic SW behavior, we