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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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134 Chapter 10<br />

Table 10-1. Execution time of H.263 enco<strong>de</strong>r system.<br />

Architecture<br />

Point-to-point interconnection<br />

Execution<br />

cycle<br />

Runtime<br />

(sec)<br />

Accuracy<br />

(%)<br />

Shared bus<br />

Execution<br />

cycle<br />

Runtime<br />

(sec)<br />

Accuracy<br />

(%)<br />

Cosimulation<br />

ILP<br />

w/o dyn. SW<br />

w/ dyn. SW<br />

Heuristic<br />

5,031,708<br />

4,684,812<br />

4,979,535<br />

4,979,535<br />

4348<br />

1.71<br />

2.23<br />

4.11<br />

100<br />

93.10<br />

98.96<br />

98.96<br />

5,151,564<br />

4,804,668<br />

5,099,391<br />

5,099,391<br />

29412<br />

10.17<br />

14.37<br />

4.23<br />

100<br />

93.27<br />

98.98<br />

98.98<br />

could enhance the accuracy from 93.10% to 98.96% <strong>for</strong> the point-to-point<br />

interconnection architecture. Similar enhancement was obtained <strong>for</strong> the other<br />

architecture. We could not obtain 100% accuracy because we did not consi<strong>de</strong>r<br />

some dynamic behaviors of task VLC and OS scheduler. In this example, the<br />

schedule obtained by the heuristic algorithm was the same as that obtained<br />

by ILP. That is why we obtained the same accuracy. Table 11-1 shows also<br />

the runtimes of cosimulation, ILP, and heuristic algorithm in seconds. In case<br />

of point-to-point interconnection, heuristic runtime is larger than that of ILP.<br />

That is because the number of no<strong>de</strong>s in ETG is so small that the complexity<br />

<strong>de</strong>pends on constants rather than the number of no<strong>de</strong>s. Note also that the<br />

cosimulation was per<strong>for</strong>med <strong>for</strong> the schedule obtained by ILP and the runtime<br />

does not inclu<strong>de</strong> the scheduling time.<br />

Then we experimented with larger examples including JPEG and IS-95<br />

CDMA. Table 10-2 shows a comparison of system execution times <strong>for</strong> different<br />

sizes of physical buffers. The third column shows the numbers of no<strong>de</strong>s<br />

in ETG and the last column shows the errors obtained by comparing with<br />

ILP optimal scheduling.<br />

As Table 10-2 shows, as the size of physical buffer gets smaller, the system<br />

execution time increases. It is due to the synchronization <strong>de</strong>lay caused by the<br />

conflicts in accessing the shared buffer. As the table shows, the ILP solutions<br />

without dynamic SW behavior give the same number of system<br />

execution cycles <strong>for</strong> three different sizes of shared buffer. This implies that<br />

without consi<strong>de</strong>ring the dynamic SW behavior, such conflicts are not<br />

accounted <strong>for</strong> during the scheduling. As shown in the table, the ILP without<br />

the dynamic SW behavior yields up to 15.13% error compared to the ILP with<br />

the dynamic SW behavior. Thus, to achieve accurate scheduling of communication<br />

and task execution, the dynamic SW behavior needs to be incorporated<br />

into the scheduling.

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