Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Analysis of HW/SW On-Chip Communication in MP SOC Design 135
Table 10-2. Execution time and errors for JPEG and IS-95 CDMA modem example.
Examples
Methods
Number
of nodes
Buffer
size
Execution
cycles
Runtime
(sec)
Errors
(%)
JPEG
ILP w/o dyn. SW
ILP w/ dyn. SW
Heuristic
ILP w/o dyn. SW
ILP w/ dyn. SW
Heuristic
ILP w/o dyn. SW
ILP w/ dyn. SW
Heuristic
30
30
30
30
30
30
30
30
30
64
64
64
32
32
32
16
16
16
141,249
147,203
147,203
141,249
153,157
153,157
141,249
165,065
165,065
200.29
11.43
0.47
194.30
70.04
0.51
196.16
15.02
0.56
–4.15
0
0
–7.78
0
0
–14.43
0
0
IS-95
CDMA
modem
ILP w/o dyn. SW
ILP w/ dyn. SW
Heuristic
ILP w/o dyn. SW
ILP w/ dyn. SW
Heuristic
49
49
49
49
49
49
64
64
64
32
32
32
1,288,079
1,305,941
1,305,941
1,333,226
1,570,771
1,570,771
156.26
471.20
4.68
161.93
482.70
5.29
–1.37
0
0
–15.13
0
0
5. CONCLUSION
On-chip communication design needs SW part design (operating system,
device driver, interrupt service routine, etc.) as well as HW part design (onchip
communication network, communication interface of processor/IP/
memory, shared memory, etc.). In this work, we tackle the problems of onchip
communication scheduling that includes SW dynamic behavior (interrupt
processing and context switching) and HW buffer sharing. To resolve
the problems, we present an ILP formulation that schedules task execution
and communication on HW/SW on-chip communication architectures as well
as a heuristic scheduling algorithm.
We applied our method to H.263 encoder, JPEG encoder, and IS-95 CDMA
systems. Our experiments show that by considering the dynamic SW behavior,
we can obtain the accuracy of scheduling of about 99%, which is more than
5%~15% improvement over naive analysis without considering the dynamic
SW behavior.
REFERENCES
1.
2.
J. Brunel, W. Kruijtzer, H. Kenter, F. Petrot, L. Pasquier, and E. Kock. “COSY Communication
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W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.
Jerayya, and M. Diaz-Nava. “Component-based Design Approach for Multicore SoCs.” In
Proceedings of Design Automation Conference, June 2002.