Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Hardware and Software Partitioning of Operating Systems 193
Example 5-1: Consider the multiprocessor SoC shown in Figure 15-5. Each
ARM processor runs at 200 MHz and has instruction and data L1 caches
each of size 64 MB. The global memory is 16 MB and requires five cycles
of latency to access the first word. A handheld device utilizing this SoC
can be used for Orthogonal Frequency Division Multiplexing (OFDM)
communication as well as other applications such as MPEG2. Initially the
device runs an MPEG2 video player. When the device detects an incoming
signal it switches to the OFDM receiver. The switching time (which
includes the time for memory management) should be short or the device
might lose the incoming message. The following table shows the sequence
of memory deallocations by the MPEG2 player and then the sequence of
memory allocations for the OFDM application.
MPEG-2 Player
2 Kbytes
500 Kbytes
5 Kbytes
1500 Kbytes
1.5 Kbytes
0.5 Kbytes
OFDM Receiver
34 Kbytes
32 Kbytes
1 Kbytes
1.5 Kbytes
32 Kbytes
8 Kbytes
32 Kbytes
We measure the execution time for the memory (de)allocations from the
application programming interface (API) level, e.g., from malloc(). In the
case where the SoCDMMU is used, the API makes special calls via
memory-mapped I/O locations to request and receive global memory from
the SoCDMMU. Thus, Figure 15-7 shows execution times which compare
software API plus hardware execution time (using the SoCDMMU) versus
only software (using optimized ARM software). Please note that the