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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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142 Chapter 11<br />

At the start of the execution, the three behaviors (tx_ppp, tx_byte and tx_bit)<br />

waits <strong>for</strong> data from the upper layer. When tx_ppp receives an IP packet from<br />

the application, it generates and sends a PPP packet to tx_byte. Tx_byte sends<br />

the PPP packet one byte at a time to tx_bit. tx_bit then transmit the data bit<br />

by bit to a serial line(bit_out). The transmission to a serial line is synchronized<br />

with the event from tx_clk (bps_event). The above mentioned process<br />

is repeated infinitely.<br />

The receiver is also divi<strong>de</strong>d into behaviors which are executed parallel. The<br />

PPP analysis behavior(rx_ppp) and the byte receive behavior(rx_byte) wait<br />

<strong>for</strong> data from the lower layer. Detection of the falling edge of the serial line<br />

<strong>for</strong> start bit <strong>de</strong>tection is per<strong>for</strong>med by the receive clock generation<br />

behavior(rx_clk_gen). When rx_clk_gen <strong>de</strong>tects the falling edge, it sends the<br />

event(bps_event) to the bit receive behavior(rx_bit) after a half cycle of the<br />

baud rate. The rx_clk_gen them continues sending the event at a cycle equal<br />

to the baud rate. When rx_bit receives the first event from rx_clk_gen, rx_bit,<br />

it <strong>de</strong>termines whether the data on the serial line is a start bit. If the data is a<br />

start bit, rx_bit fetches the data on the serial line synchronized with the event<br />

from rx_clk_gen. If the data is not a start bit, tx_bit resets rx_clk_gen <strong>for</strong><br />

further <strong>de</strong>tection of a start bit. rx_bit also resets rx_clk_gen after receiving 1<br />

byte of data. The reset functionality of rx_clk_gen was realized using try-trapinterrupt<br />

statement, wrapper behavior and dummy behavior. In the statement

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