Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

224 Chapter 17
vidual serve for the generation of the conditions of the splitting-if and lead
to the minimization of if-statement executions.
4. BENCHMARKING RESULTS
All techniques presented here are fully implemented using the SUIF [24],
Polylib [23] and PGAPack [14] libraries. Both GA’s use the default parameters
provided by [14] (population size 100, replacement fraction 50%, 1,000
iterations). Our tool was applied to three multimedia programs. First, a cavity
detector for medical imaging (CAV [3]) having passed the DTSE methodology
[9] is used. We apply loop nest splitting to this transformed application for
showing that we are able to remove the overhead introduced by DTSE without
undoing the effects of DTSE. The other benchmarks are the MPEG4 full
search motion estimation (ME [8], see Figure 17-1) and the QSDPCM algorithm
[22] for scene adaptive coding.
Since all polyhedral operations [23] have exponential worst case complexity,
loop nest splitting also is exponential overall. Yet, the effective
runtimes of our tool are very low, between 0.41 (QSDPCM) and 1.58 (CAV)
CPU seconds are required for optimization on an AMD Athlon (1.3 GHz).
For obtaining the results presented in the following, the benchmarks are
compiled and executed before and after loop nest splitting. Compilers are
always invoked with all optimizations enabled so that highly optimized code
is generated.
Section 4.1 illustrates the impacts of loop nest splitting on CPU pipeline
and cache behavior. Section 4.2 shows how the runtimes of the benchmarks
are affected by loop nest splitting for ten different processors. Section 4.3
shows in how far code sizes increase and demonstrates that our techniques
are able to reduce the energy consumption of the benchmarks considerably.
4.1. Pipeline and Cache Behavior
Figure 17-4 shows the effects of loop nest splitting observed on an Intel
Pentium III, Sun UltraSPARC III and a MIPS R10000 processor. All CPUs
have a single main memory but separate level 1 instruction and data caches.
The off-chip L2 cache is a unified cache for both data and instructions in all
cases.
To obtain these results, the benchmarks were compiled and executed on the
processors while monitoring performance-measuring counters available in the
CPU hardware. This way, reliable values are generated without using erroneous
cache simulators. The figure shows the performance values for the
optimized benchmarks as a percentage of the un-optimized versions denoted
as 100%.
The columns Branch Taken and Pipe stalls show that we are able to
generate a more regular control flow for all benchmarks. The number of taken