Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

130 Chapter 10
The delay of communication interface is given as a function of data
size [14].
The delay of on-chip communication network is
where is a constant delay of transferring a single data item and
is a delay caused by the contention of access to the communication network
(e.g. bus contention).
and can be calculated during task/communication scheduling,
which is explained in the next subsection.
3.2.2. ILP for scheduling communication nodes and tasks
In scheduling tasks and communication transactions, we need to respect data
dependency between tasks and to resolve resource contention on the target
architecture. In the target architecture, there are three types of resource that
are shared by tasks and communications: processors, communication networks
(e.g. on-chip buses), and physical buffers. Therefore, we model the scheduling
problem with (1) data dependency constraints between tasks, (2) constraints
that represent resource contention and (3) an objective function that
aims to yield the minimum execution time of the task graph.
3.2.2.1. Data dependency constraints
In the ETG, data and communication dependency is represented by directed
edges. For every edge from node to node the following inequalities are
satisfied.
3.2.2.2. Resource contention constraints
Processor and on-chip communication network. Processor contention and
on-chip communication network contention are similar in that the contentions
occur when two or more components are trying to access the same resource
(processor or on-chip communication network) at the same time. To formulate
the processor contention constraints in the ILP, first we find a set of task
nodes that are mapped on the same processor. For the task set, the processor
contention occurs when two tasks, and try to use the same processor
simultaneously. To prevent such a processor contention, we need to satisfy
or
The same concept applies to the on-chip
communication networks such as on-chip buses and point-to-point interconnections.
Physical buffer contention constraints. Physical buffer contention constraints
are different from those of processor and on-chip communication network