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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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102 Chapter 8<br />

the slave access of a bus channel as show on Figure 8-4. These compositions<br />

can be the beginning of a methodology to refine the communication of a<br />

system and progressively going from a purely functional mo<strong>de</strong>l to an architectural<br />

timed mo<strong>de</strong>l. A first step would be to <strong>de</strong>tach some functions of the<br />

sequential algorithm into modules that prefigures the architecture. Then<br />

regarding the iteration on the data, between the functions, one may start ahead<br />

the <strong>de</strong>tached function as soon as it has enough data to start with, <strong>for</strong> example<br />

a subset of a picture. This is quite the same i<strong>de</strong>a of setting a pipeline communication,<br />

so one may then prepare a communication through a FIFO channel<br />

to synchronize the execution flow of the <strong>de</strong>tached functions. Note that the<br />

FIFO can also store control so far these a operation calls which are stacked.<br />

At this stage we a system level mo<strong>de</strong>l very similar to what we can have with<br />

SDL. We can introduce timing at this stage to analyze the parallelism of the<br />

all system. Then one may <strong>de</strong>ci<strong>de</strong> the partitioning of the system and thus share<br />

the communication resources. Hence a bus can refine the FIFO communications,<br />

some data passing can be referring a shared memory. This is generally<br />

the impact of hardware level resource sharing which is ignored by the other<br />

specification languages which stops their analysis at the FIFO level.<br />

2.1.3. Dynamic pattern<br />

The Figure 8.5 shows how the protocol between the channel and its master<br />

and slave accesses is played.<br />

A slave registers, at the end of elaboration phase, its provi<strong>de</strong>d operations<br />

to the channel through the slave access. These operations are i<strong>de</strong>ntified with<br />

a key ma<strong>de</strong> of an address, and an optional qualifier, if the address is overloa<strong>de</strong>d<br />

by the slave.<br />

Then a master can initiate a slave operation by invocating the sibling<br />

operation of its master access. The master access retrieves first the operation<br />

in the <strong>de</strong>coding step and then notify the channel to execute the pre-transactions,<br />

be<strong>for</strong>e the channel allows it to effectively reach the slave operation.<br />

Once the guar<strong>de</strong>d operation is done, the master access notifies the posttransaction<br />

transactions.

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