Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

314 Chapter 23
gies for the typical internal junction temperatures in a chip [2]. We assumed
a 20 msec resynchronization latency (a conservative estimate) to bring a turned
off processor (and its caches) into the full operational mode. We also assumed
a simple synchronization mechanism where each processor updates a bit in a
globally shared and protected location. When a processor updates its bit‚ it
waits for the other processors to update their bits. When all processor update
their bits‚ all processors continue with their parallel execution. Our energy
calculation also includes the energy consumed by the processors during
synchronization.
For each processor‚ both data and instruction caches are 8 KB‚ 2-way
set-associative with 32 byte blocks and an access latency of 1 cycle. The
on-chip shared memory is assumed to be 1 MB with a 12 cycle access latency.
All our energy values are obtained using the 0.1-micron process technology.
The cache hit and miss statistics are collected at runtime using the performance
counters in a Sun Spare machine‚ where all our simulations have been
performed.
We used a set of eight benchmarks to quantify the benefits due to our
runtime parallelization strategy‚ Img is an image convolution application.
Cholesky is a Cholesky decomposition program. Atr is a network address
translation application. SP computes the all-nodes shortest paths on a given
graph. Encr has two modules. The first module generates a cryptographicallysecure
digital signature for each outgoing packet in a network architecture.
The second one checks the authenticy of a digital signature attached to an
incoming message. Hyper simulates the communication activity in a distributed-memory
parallel architecture. wood implements a color-based visual
surface inspection method. Finally‚ Usonic is a feature-based object estimation
algorithm. The important characteristics of these benchmarks are given
in Table 23-2. The last two columns give the execution cycles and the energy
consumptions (in the processor core‚ caches‚ and the shared memory) when
our applications are executed using a single processor.
Table 23-2. Benchmark codes used in the experiments and their important characteristics.
Benchmark
Input
Cycles
Energy
Img
Cholegky
Atr
SP
Encr
Hyper
Wood
Usonic
263.1 KB
526.0 KB
382.4 KB
688.4 KB
443.6 KB
451.1 KB
727.6 KB
292.9 KB
16526121
42233738
19689554
268932537
28334189
25754072
362069719
9517606
18.51 mJ
53.34 mJ
24. 88 mJ
91.11 mJ
72.55 mJ
66.80 mJ
90.04 mJ
22.93 mJ