Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

240 Chapter 18
several heuristics can be used. In line 16, we restructure the process codes
(i.e., tile them).
3. EXPERIMENTS
3.1. Implementation and experimental methodology
We evaluate our data space oriented process scheduling strategy using a simple
in-house simulator. This simulator takes as input a program (represented as a
process dependence graph), a scheduling order, a data cache configuration
(associativity, cache size, and line size), and cache simulator as parameters,
and records the number of cache hits/misses in the data cache and execution
cycles. For cache simulations, we used a modified version of Dinero III [6].
The code transformations are implemented using the SUIF compiler infrastructure
from Stanford University [1] and the Omega Library [2].
3.2. Benchmarks
Our benchmark suite contains five large array-intensive embedded applications.
Encr implements the core computation of an algorithm for digital
signature for security. It has two modules, each with eleven processes. The
first module generates a cryptographically-secure digital signature for each
outgoing packet in a network architecture. User requests and packet send
operations are implemented as processes. The second module checks the
digital signature attached to an incoming message.
Usonic is a feature-based object estimation kernel. It stores a set of encoded
objects. Given an image and a request, it extracts the potential objects of
interest and compares them one-by-one to the objects stored in the database
(which is also updated). Im-Unit is an image processing package that works
with multiple image formats. It has built-in functions for unitary image
transformations, noise reduction, and image morphology. MPC is a medical
pattern classification application that is used for interpreting electrocardiograms
and predicting survival rates. Im-An is an image analysis algorithm that
is used for recognizing macromolecules.
3.3. Results
In Figure 18-5, we divide the execution time of each application into three
sections: the time spent in CPU by executing instructions, the time spent in
cache accesses, and the time spent in accesses to the off-chip memory. We
clearly see from this graph that the off-chip memory accesses can consume
significant number of memory cycles. To understand this better, we give in
Figure 18-6 the execution time breakdown for the processes of the MPC
benchmark. We observe that each process spends a significant portion of its