Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

194 Chapter 15
speedups shown exceed 10× when compared to GCC libc memory management
functions [14, 15, 18].
An area estimate for Figure 15-5 indicates that, excluding the
SoCDMMU, 154.75 million transistors are used [18]. Since the hardware
area used by the SoCDMMU logic is approximately 7,500 transistors,
30 K transistors are needed for a four processor configuration such as
Figure 15-5. An additional 270 K transistors are needed for memory used
by the SoCDMMU (mainly for virtual to physical address translation) for
the example above [18]. Thus, for 300 K (0.19%) extra chip area in this
154.75 million transistor chip, a 4–10× speedup in dynamic memory allocation
times is achieved.
4.2. The SoCLC (RTOS1 vs. RTOS3)
The System-on-a-Chip Lock Cache (SoCLC) removes lock variables from the
memory system and instead places them in a special on-chip “lock cache.”
Figure 15-8 shows a sample use of the SoCLC in a 4-processor system.
The right-hand-side of Figure 15-8 shows that the SoCLC keeps track of
lock requestors through and generates interrupts to wake up the next
in line (in FIFO or priority order) when a lock becomes available [11–13].
The core idea of the SoCLC is to implement atomic test-and-set in an SoC
without requiring any changes to the processor cores used.