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Data Space Oriented Scheduling 241 execution cycles in waiting for off-chip memory accesses to complete. Since we know that there is significant amount of data reuse between successively scheduled processes of this application, the data presented by the graph in Figure 18-6 clearly indicates that the data cache is not utilized effectively. That is, the data left by a process in the data cache is not reused by the next process (which means poor data cache behavior). To check whether this trend is consistent when time quanta is modified, we performed another set of experiments. The graph in Figure 18-7 shows the execution time breakdown for different time quanta. The values shown in this graph are the values averaged over all benchmarks in our experimental suite. One can see that although increasing quanta leads to better cache locality, the trends observed above still holds (in fact, memory stall cycles constitute nearly 25% of the total execution cycles with our largest quanta). Figure 18-8 presents the execution time savings for all benchmarks with different cache capacities. These results indicate that even with large data cache sizes (e.g., 32 KB and 64 KB), our strategy brings significant execution time benefits. As expected, we perform better with small cache sizes. Considering the fact that data set sizes keep increasing, we expect that the results with small cache sizes indicate future trends better.
242 Chapter 18 In the last set of experiments, we compared our strategy (denoted DSOS) in Figure 18-9) with four different scheduling strategies using our default configuration. Method1 is a locality-oriented process scheduling strategy. It restructures process codes depending on the contents of the data cache. Method2 is like Method1 except that it also changes the original scheduling order in an attempt to determine the best process to schedule next (i.e., the
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Page 236 and 237: Chapter 17 CONTROL FLOW DRIVEN SPLI
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Page 252 and 253: Chapter 18 DATA SPACE ORIENTED SCHE
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Page 266 and 267: Chapter 19 COMPILER-DIRECTED ILP EX
Page 268 and 269: Compiler-Directed ILP Extraction 24
Page 282 and 283: Chapter 20 STATE SPACE COMPRESSION
Page 284 and 285: State Space Compression in History
Page 296 and 297: Chapter 21 SIMULATION TRACE VERIFIC
Page 298 and 299: Simulation Trace Verification for Q
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Page 310 and 311: Chapter 22 EFFICIENT POWER/PERFORMA
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Efficient Power/Performance Analysi
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Chapter 23 DYNAMIC PARALLELIZATION
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Dynamic Parallelization of Array 30
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Chapter 24 SDRAM-ENERGY-AWARE MEMOR
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SDRAM-Energy-Aware Memory Allocatio
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PART VII: SAFE AUTOMOTIVE SOFTWARE
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Chapter 25 SAFE AUTOMOTIVE SOFTWARE
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Safe Automotive Software Developmen
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PART VIII: EMBEDDED SYSTEM ARCHITEC
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Chapter 26 EXPLORING HIGH BANDWIDTH
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Exploring High Bandwidth Pipelined
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Chapter 27 ENHANCING SPEEDUP IN NET
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Enhancing Speedup in Network Proces
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Chapter 28 ON-CHIP STOCHASTIC COMMU
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On-Chip Stochastic Communication 37
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Chapter 29 HARDWARE/SOFTWARE TECHNI
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HW/SW are Techniques for Improving
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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Embedded Software for SoC - Grupo de MecatrÃ´nica EESC/USP

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