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Rapid Configuration & Instruction Selection for an ASIP 409 call graph of the application for each Xtensa processor. Then we calculate the effectiveness of the processor for this application by considering total cycle-count‚ clock period‚ and the area of each configurable processor. The effectiveness of the Xtensa processor i‚ is defined as: This factor indicates a processor is most effective when it has the smallest chip size with the smallest execution time (cycle-count CC multiplied by the Table 30-1. Notations for algorithm. Notation Speedup_TIEij Area_TIEj Pij CCi Clock_Periodi Latencyj Selectedi() Descriptions Area in gate for processor i Speedup ratio of TIE instruction j in processor I Area in gate of TIE instruction j Percentage of cycle-count for function j in processor i Total cycle-count spent in processor i Clock period of processor i Latency of TIE instruction j Array stores selected TIE instructions in processor i
410 Chapter 30 clock period) of an application. This factor calculates the ratio of performance per area for each processor‚ and our methodology selects the processor with the highest performance per area ratio that falls within the area constraint. This factor may not select the processor with the best performance. Note‚ that “Area_Core” is not only an optimization goal but may also be a (hard) constraints. Next‚ the methodology focuses on selecting specific TIE instructions. The selection of a specific TIE instruction is based on the area‚ speedup ratio‚ latency (maximum clock period in all TIE instructions and configured processor)‚ and percentage of total cycle-count for the TIE instruction. We define the gradient of TIE instruction j in Xtensa processor k as: This factor indicates that the performance gain per area of an application when the TIE instruction is implemented in the Xtensa processor. For example‚ if an application spent 30% of the time calling function X and 20% of the time calling function Y‚ two TIE instructions‚ say and are implemented to replace software function call X and software function call Y. The speedup of TIE instructions is 4 times and 6 times for and respectively‚ and the area for the implemented TIE instructions are 3000 gates and 4000 gates respectively. The latency value (the clock period) for both instructions is the same. The gradient of functional units is 0.0004 and 0.0003 for and This means that will be considered for implementation in the processor before This example shows that the overall performance gain of an application will be the same whether or is implemented. Since has a smaller area‚ is selected before Equation 2 uses the remaining area effectively by selecting the specific TIE instruction with largest performance improvement per area. This is a greedy approach to obtain the largest performance improvement per area. This greedy approach proved to be effective and efficient‚ though may not prove to be as efficient for another application. In the last section‚ after TIE instructions are selected‚ an estimation of execution time is calculated. The estimation of execution time for an Xtensa processor k with a set of selected TIE instruction (from 1 to j) is defined as: where is the original total cycle-count of an application in processor k. The first part of the equation calculates the cycle-count of an application‚ then it multiples with the maximum latency between TIE instructions. Maximum latency is the maximum clock period value of all the TIE instructions and configured processor.
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Chapter 16 EMBEDDED SW IN DIGITAL A
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Embedded SW in Digital AM-FM Chipse
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Embedded SW in Digital AM-FM Chipse
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PART V: SOFTWARE OPTIMISATION FOR E
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Chapter 17 CONTROL FLOW DRIVEN SPLI
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Control Flow Driven Splitting of Lo
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Chapter 18 DATA SPACE ORIENTED SCHE
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Data Space Oriented Scheduling 233
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Chapter 19 COMPILER-DIRECTED ILP EX
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Compiler-Directed ILP Extraction 24
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Chapter 20 STATE SPACE COMPRESSION
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State Space Compression in History
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Chapter 21 SIMULATION TRACE VERIFIC
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Simulation Trace Verification for Q
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PART VI: ENERGY AWARE SOFTWARE TECH
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Chapter 22 EFFICIENT POWER/PERFORMA
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Efficient Power/Performance Analysi
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Chapter 23 DYNAMIC PARALLELIZATION
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Dynamic Parallelization of Array 30
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Chapter 24 SDRAM-ENERGY-AWARE MEMOR
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SDRAM-Energy-Aware Memory Allocatio
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PART VII: SAFE AUTOMOTIVE SOFTWARE
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Chapter 25 SAFE AUTOMOTIVE SOFTWARE
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Safe Automotive Software Developmen
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PART VIII: EMBEDDED SYSTEM ARCHITEC
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Chapter 26 EXPLORING HIGH BANDWIDTH
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Exploring High Bandwidth Pipelined
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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Embedded Software for SoC - Grupo de MecatrÃ´nica EESC/USP

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