Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Control Flow Driven Splitting of Loop Nests 227
These increases are not serious, since the added energy required for storing
these instructions is compensated by the savings achieved by loop nest splitting.
Figure 17-6b shows the evolution of memory accesses and energy consumption
using an instruction-level energy model [21] for the ARM7 core
considering bit-toggles and offchip-memories and having an accuracy of 1.7%.
Column Instr Read shows reductions of instruction memory reads of
23.5% (CAV) – 56.9% (ME). Moreover, our optimization reduces data
memory accesses significantly. Data reads are reduced up to 65.3% (ME). For
QSDPCM, the removal of spill code reduces data writes by 95.4%. In contrast,
the insertion of spill code for CAV leads to an increase of 24.5%. The sum
of all memory accesses (Mem accesses) drops by 20.8% (CAV) – 57.2%
(ME).
Our optimization leads to large energy savings in both the CPU and its
memory. The energy consumed by the ARM core is reduced by 18.4% (CAV)
– 57.4% (ME), the memory consumes between 19.6% and 57.7% less energy.
Total energy savings by 19.6% – 57.7% are measured. These results
demonstrate that loop nest splitting optimizes the locality of instructions and
data accesses simultaneously as desired by Kim, Irwin et al. [11]
Anyhow, if code size increases (up to a rough theoretical bound of 100%)
are critical, our algorithms can be changed so that the splitting-if is placed in
some inner loop. This way, code duplication is reduced at the expense of lower
speed-ups, so that trade-offs between code size and speed-up can be realized.
5. CONCLUSIONS
We present a novel source code optimization called loop nest splitting which
removes redundancies in the control flow of embedded multimedia applications.
Using polytope models, code without effect on the control flow is
removed. Genetic algorithms identify ranges of the iteration space where all
if-statements are provably satisfied. The source code of an application is
rewritten in such a way that the total number of executed if-statements is
minimized.
A careful study of 3 benchmarks shows significant improvements of
branching and pipeline behavior. Also, caches benefit from our optimization
since I- and D-cache misses are reduced heavily (up to 68.5%). Since accesses
to instruction and data memory are reduced largely, loop nest splitting thus
leads to large power savings (19.6%–57.7%). An extended benchmarking
using 10 different CPUs shows mean speed-ups of the benchmarks by
23.6%–62.1%.
The selection of benchmarks used in this article illustrates that our optimization
is a general and powerful technique. Not only typical real-life
embedded code is improved, but also negative effects of other source code
transformations introducing control flow overheads into an application are
eliminated. In the future, our analytical models are extended for treating more