Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Hardware and Software Partitioning of Operating Systems 201
Second, Archi_gen generates (ii) the code for wiring up the SoCLC system
(including all buses). Third, Archi_gen generates (iii, see Figure 15-12) the
instantiation code according to the instantiation type of the hardware
modules chosen. In this step, Archi_gen also generates instantiation code
for the appropriate number of PEs according to the user selection of the
number of PEs in the tool. In this example, Archi_gen generates code for
MPC750 instantiation four times (since the architecture has four MPC750s).
Fourth, Archi_gen extracts the initialization code (needed for test) for
necessary signals according to the SoCLC initialization description. Finally,
a Verilog header file containing an SoCLC system hardware architecture
is made.
6. EXPERIMENTAL RESULTS
Figure 15-4 showed six possible hardware/software RTOS configurations
generated by the Framework. Here, we use the word “system” to refer to
an SoC architecture with an RTOS. Each SoC architecture has four PEs and
additional hardware modules – for example, the modules shown in Figure
15-8 (and described in Section 5.2.3). The first configuration (RTOS1) in
Figure 15-4, marked as “SW RTOS w/ sem, dmm” (with semaphores and
dynamic memory management software), was used in Sections 4.1 and 4.2
for comparisons with the second configuration (RTOS2) and the third
(RTOS3), namely, systems containing the SoCDMMU and SoCLC, respectively.
Comparisons involved the fourth configuration (RTOS4), “SW RTOS
+ SoCDDU” which is a system utilizing SoCDDU, and the fifth configura-