Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

126 Chapter 10
On-chip communication design considering both SW and HW
communication architectures
Most of previous on-chip communication design methods focus on HW communication
architecture design, such as bus topology design, determining bus
priorities, and DMA size optimization [3–7]. A few studies consider the SW
communication architecture in on-chip communication design [5, 8]. In [5],
Ortega and Borriello presented a method of SW architecture implementation.
In [8], Knudsen and Madsen considered device driver runtime (which depends
statically on the size of transferred data) to estimate on-chip communication
runtime. However, the behavior of SW communication architecture is
dynamic. The dynamism includes interrupt processing, context switching, etc.
Since the overhead of interrupt and that of context switching can often
dominate embedded SW runtime, they can significantly affect the total
performance of HW/SW on-chip communication. In this work, we take into
account the dynamic behavior of SW communication architecture in scheduling
on-chip communication (Problem 1).
Physical communication data storage: a physical communication buffer
sharing problem
In MP SoCs, multiple processors, other IPs and memory components communicate
with each other requiring a data storage, i.e. physical communication
buffer, to enable the communication. It is often the case that the physical
communication buffer can take a significant portion of chip area. Especially,
in the case of multimedia systems such as MPEG 2 and 4, the overhead of
physical communication buffer can be significant due to the requirement of
large-size data communication between components on the chip. Therefore,
to reduce the chip area, we need to reduce the size of the physical communication
buffers of on-chip communication architecture. In our work, for the
reduction, we take into account the sharing of the physical communication
buffers by different communications in scheduling on-chip communication
(Problem 2).
2. MOTIVATION
Figure 10-1 shows a simple task graph and its mapping on a target architecture.
The three tasks in the graph are mapped on a microprocessor and a DSP.
The two edges (communication buffers) are mapped on a shared memory in
the target architecture. Figure 10-1(b), (c), and (d) shows Gantt charts for three
cases of scheduling task execution and communication.
In Figure 10-1(b), we assume that the two edges mapped on the shared
memory do not share their physical buffers with each other. Thus, two physical
buffers on the shared memory occupy separate regions of the shared memory.
Figure 10-1(b) exemplifies the execution of the system in this case. First,
task T1 executes and writes its output on its output physical buffer on the