Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

22 Chapter 2
range. Therefore‚ no task will ever find a previously executed instruction in
the cache‚ since other tasks will have filled the cache completely between two
executions. However‚ Table 2-2 indicates that RTOS functions benefit from
the cache‚ both because they may contain loops‚ and because they can be called
multiple times shortly after each other‚ and their code thus is not replaced
in-between calls.
Again‚ we used the setup described in Section 5.1 to perform several
experiments to be checked against our analysis. We ran experiments executing
the code from the external memory‚ both with enabled and disabled cache (see
also Figure 2-3). The results are shown in Table 2-3. Task C has the highest‚
task A the lowest priority. The first and second columns show the worst case
response times obtained by applying the above formula. In column one‚ worst
case RTOS overhead with cache from Table 2-2 was used‚ in column two‚
worst case RTOS overhead without cache. The third and fourth columns show
a range of measured response times during test-runs with and without cache.
As can be seen‚ even in the simple 3-task system presented here‚ there is
a large response time variation between measurements. The size of the
response time intervals becomes larger with decreasing task priority (due to
more potential interrupts by higher priority tasks)‚ but even the highest priority
task experiences response time jitter due to the varying number of interrupts
by RTOS functions running at even higher priority.
Our calculated worst case response times conservatively bound the observed
behavior. The calculated worst case response times are only about 6% higher
than the highest measured values‚ indicating the good tightness analysis can
achieve if effects from scheduling‚ RTOS overhead‚ single process execution
times and caches are all considered. Results would be even better with a more
detailed RTOS model.
Another observation is that the cache and memory architecture in not welladjusted
for our target applications. We are currently looking into a TriCore
version with 16 k 2-way associative cache for the production ECU. However‚
due to the characteristics of engine control code‚ we do not expect that single
processes will benefit from a different cache architecture. Likewise‚ 16 k of
cache are still by far too small to avoid complete replacement of process
code between two activations of the same process.
At this point‚ we are still confined to single ECU applications.
Table 2-3. Task response times.
Task
Calculated worstcase
response
times (w/ cache)
Calculated worst-)
case response
times (w/o cache
Measured
response time
(w/ cache)
Measured
response time
(w/o cache)
A
B
C