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Dynamic Parallelization of Array 317 whereas the remaining nests do not. Since the third nest of this application is the one with the largest execution time‚ it dominates the overall energy-delay product‚ leading to some gain when the entire application is considered. Hyper‚ on the other hand‚ benefits from the history based training. The last two bars Figure 23-5 show‚ for each nest‚ the normalized energy-delay product due to our strategy without and with past history information. Recall from Section 1.3.0 that when the history information is used‚ we can eliminate the training overheads in successive visits. The results shown in the figure clearly indicate that all nests in this application take advantage of history information‚ resulting in a 9% improvement in the energy-delay product as compared to our strategy without history information. 5. CONCLUDING REMARKS On-chip multiprocessing is an attempt to speedup applications by exploiting inherent parallelism in them. In this study‚ we have made three major contributions. First‚ we have presented a runtime loop parallelization strategy for on-chip multiprocessors. This strategy uses the initial iterations of a given loop to determine the best number of processors to employ in executing the remaining iterations. Second‚ we have quantified benefits of our strategy using a simulation environment and showed how its behavior can be improved by being more aggressive in determining the best number of processors. Third‚ we have demonstrated that the overheads associated with our approach can be reduced using past history information about loop executions.
318 Chapter 23 REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. R. Balasubramonian et al. “Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures.” In Proceedings of 33rd International Symposium on Micro-architecture‚ pp. 245—257‚ December 2000. A. Chandrakasan et al. “Design of High-Performance Microprocessor Circuits.” IEEE Press‚ 2001. DAC’02 Sessions: “Design Methodologies Meet Network Applications” and “System on Chip Design”‚ New Orleans‚ LA‚ June 2002. http://industry.java.sun.com/javanews/stories/story2/0‚ 1072‚32080‚00.html A. Iyer and D. Marculescu. “Power-Aware Micro-architecture Resource Scaling.” In Proceedings of IEEE Design‚ Automation‚ and Test in Europe Conference‚ Munich‚ Germany‚ March 2001. I. Kadayif et al. “An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors.” In Proceedings of Design Automation Conference‚ New Orleans‚ LA‚ June 2002. K. S. McKinley. Automatic and Interactive Parallelization‚ PhD Dissertation‚ Rice University‚ Houston‚ TX‚ April 1992. S. Wilton and N. P. Jouppi. “CACTI: An Enhanced Cycle Access and Cycle Time Model.” IEEE Journal of Solid-State Circuits‚ pp. 677–687‚ 1996. M. Wolfe. High Performance Compilers for Parallel Computing. Addison-Wesley Publishing Company‚ 1996. W. Ye et al. “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool.” In Proceedings of the 37th Design Automation Conference‚ Los Angeles‚ CA‚ June‚ 2000.
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Chapter 16 EMBEDDED SW IN DIGITAL A
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Embedded SW in Digital AM-FM Chipse
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Embedded SW in Digital AM-FM Chipse
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PART V: SOFTWARE OPTIMISATION FOR E
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Chapter 17 CONTROL FLOW DRIVEN SPLI
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Control Flow Driven Splitting of Lo
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Chapter 18 DATA SPACE ORIENTED SCHE
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Data Space Oriented Scheduling 233
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Chapter 19 COMPILER-DIRECTED ILP EX
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Compiler-Directed ILP Extraction 24
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Chapter 20 STATE SPACE COMPRESSION
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State Space Compression in History
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State Space Compression in History
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Enhancing Speedup in Network Proces
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Chapter 28 ON-CHIP STOCHASTIC COMMU
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On-Chip Stochastic Communication 37
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Chapter 29 HARDWARE/SOFTWARE TECHNI
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HW/SW are Techniques for Improving
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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