Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

4 Chapter 1
of RTOS models is becoming strategic inside hardware/software co-design
environments.
This work‚ based on Cadence Virtual Component Co-design (VCC) environment
[3]‚ shows a design flow to automatically generate and evaluate
software – including a RTOS layer – for a target architecture. Starting from
executable specifications‚ an untimed model of an existing SoC is defined and
validated by functional simulations. At the same time an architectural model
of the target system is defined providing a platform for the next design phase‚
where system functionalities are associated with a hardware or software
architecture element. During this mapping phase‚ each high-level communication
between functions has to be refined choosing the correct protocol from
a set of predefined communication patterns. The necessary glue for connecting
together hardware and software blocks is generated by the interface synthesis
process.
At the end of mapping‚ software estimations have been performed before
starting to directly simulate and validate generated code to a board level prototype
including our target chip.
Experimental results show a link to implementation consistency with an
overhead of about 11.8% in term of code execution time. Performance estimations
compared against actual measured performances of the target system
show an accuracy error less than 1%.
2. SPEECH RECOGNITION SYSTEM DESCRIPTION
A single-chip‚ processor-based system with embedded built-in speech recognition
capabilities has been used as target in this project. The functional block
diagram of the speech recognition system is shown in Figure 1-1. It is basically
composed by two hardware/software macro-blocks.
The first one‚ simply called front-end (FE)‚ implements the speech acquisition
chain. Digital samples‚ acquired from an external microphone‚ are
processed (Preproc) frame by frame to provide a sub-sampled and filtered
speech data to EPD and ACF blocks. While ACF computes the auto-correlation
function‚ EPD performs an end-point detection algorithm to obtain
silence-speech discrimination.
ACF concatenation with the linear predictive cepstrum block (LPC) translates
each incoming word (i.e. a sequence of speech samples) into a variablelength
sequence of cepstrum feature vectors [4]. Those vectors are then
compressed (Compress) and transformed (Format) in a suitable memory structure
to be finally stored in RAM (WordRam).
The other hardware/software macro-block‚ called back-end (BE)‚ is the SoC
recognition engine where the acquired word (WordRAM) is classified comparing
it with a previously stored database of different words (Flash Memory).
This engine‚ based on a single-word pattern-matching algorithm‚ is built
by two nested loops (DTW Outloop and DTW Innerloop) that compute L1 or