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Compiler-Directed ILP Extraction 255 Certain special purpose architectures, like transport triggered architectures, as proposed in [1], are primarily programmed by scheduling data transports, rather than the CDFG’s operations themselves. Code generation for such architectures is fundamentally different, and harder than code generation for the standard VLIW/EPIC processors assumed in this paper, see [2]. 6. EXPERIMENTAL RESULTS Compiler algorithms reported in the literature either jointly address speculation and modulo scheduling but do not consider clustered machines, or consider modulo scheduling on clustered machines but cannot handle conditionals i.e., can only address straight code, with no notion of control speculation (see Section 5). Thus, the novelty of our approach makes it difficult to experimentally validate our results in comparison to previous work. We have however devised an experiment that allowed us to assess two of the key contributions of this paper, namely, the proposed load-balancing-driven incremental control speculation and the phasing for the complete optimization problem. Specifically, we compared the code generated by our algorithm to code generated by a baseline algorithm that binds state of the art predicated code (with predicate promotion only) [6] to a clustered machine and then modulo schedules the code. In order to ensure fairness, the baseline algorithm uses the same binding and modulo scheduling algorithms implemented in our framework. We present experimental results for a representative set of critical loop kernels extracted from the MediaBench [5] suite of programs and from TI’s benchmark suite [17] (see Table 19-1). The frequency of execution of the Table 19-1. Kernel characteristics. Kernel Lsqsolve Csc Shortterm Store Ford Jquant Huffman Add Pixel1 Pixel2 Intra Nonintra Vdthresh8 Collision Viterbi Benchmark Rasta/Lsqsolve Mpeg Gsm Mpeg2dec Rasta Jpeg Epic Gsm Mesa Mesa Mpeg2enc Mpeg2enc TI suite TI suite TI suite Main Inner Loop from Function eliminate() csc() fast_Short_term_synthesis_filtering() conv422to444() FORD1() find_nearby_colors() encode_stream() gsm_div() gl_write_zoomed_index_span() gl_write_zoomed_stencil_span() iquant1_intra() iquant1 _non_intra()
256 Chapter 19 selected kernels for typical input data sets was determined to be significant. For example, the kernel Lsqsolve from the least squares solver in the rasta distribution, one of the kernels where OPT-PH performs well, takes more than 48% of total time taken by the solver. Similarly, Jquant, the function find_nearby_colors() from the Jpeg program, yet another kernel where OPT-PH performs well, takes more than 12% of total program execution time. The test kernels were manually compiled to a 3-address like intermediate representation that captured all dependences between instructions. This intermediate representation together with a parameterized description of a clustered VLIW datapath was input to our automated optimization tool (see Figure 19-4). Four different clustered VLIW datapath configurations were used for the experiments. All the configurations were chosen to have relatively small clusters since these datapath configurations are more challenging to compile to, as more data transfers may need to be scheduled. The FU’s in each cluster include Adders, Multipliers, Comparators, Load/Store Units and Move Ports. The datapaths are specified by the number of clusters followed by the number of FU’s of each type, respecting the order given above. So a configuration denoted 3C: |1|1|1|1|1| specifies a datapath with three clusters, each cluster with 1 FU of each type. All operations are assumed to take 1 cycle except Read/Write, which take 2 cycles. A move operation over the bus takes 1 cycle. There are 2 intercluster buses available for data transfers. Detailed results of our experiments (15 kernels compiled for 4 different datapath configurations) are given in Table 19-2. For every kernel and datapath configuration, we present the performance of modulo scheduled standard predicated code with predicate promotion (denoted Std. Pred-MOD) compared to that of code produced by our approach (denoted OPT-PH-MOD). As can be seen, our technique consistently produces shorter initiation intervals and gives large increases in performance, upto a maximum of 68.2%. This empirically demonstrates the effectiveness of the speculation criteria and load balancing scheme developed in the earlier Sections. The breaking of control dependences and efficient redistribution of operation load both over their time frames as well as across clusters, permits dramatic decreases in initiation interval. Finally, although the results of our algorithm cannot be compared to results produced by high level synthesis approaches (as discussed in Section 5), we implemented a modified version of the list scheduling algorithm proposed in [7], that performed speculation “on the fly”, and compared it to our technique. Again, our algorithm provided consistently faster schedules with performance gains upto 57.58%. 7. CONCLUSIONS The paper proposed a novel resource-aware algorithm for compiler-directed ILP extraction targeting clustered EPIC machines. In addition to extracting
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EMBEDDED SOFTWARE FOR SoC
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Embedded Software for SoC Edited by
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DEDICATION This book is dedicated t
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TABLE OF CONTENTS Dedication Conten
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Table of Conents Chapter 16 EMBEDDE
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Table of Conents Chapter 33 ADAPTIV
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PREFACE The evolution of electronic
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INTRODUCTION Embedded software is b
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Introduction xvii software consists
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Introduction xix Energy-aware techn
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PART I: EMBEDDED OPERATING SYSTEMS
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Chapter 1 APPLICATION MAPPING TO A
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Application Mapping to a Hardware P
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Chapter 2 FORMAL METHODS FOR INTEGR
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Formal Methods for Integration of A
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Chapter 3 LIGHTWEIGHT IMPLEMENTATIO
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Lightweight Implementation of the P
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Chapter 4 DETECTING SOFT ERRORS BY
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Detecting Soft Errors by a Purely S
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PART II: OPERATING SYSTEM ABSTRACTI
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Chapter 5 RTOS MODELING FOR SYSTEM
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RTOS Modeling for System Level Desi
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Chapter 6 MODELING AND INTEGRATION
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Modeling and Integration of Periphe
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Chapter 7 SYSTEMATIC EMBEDDED SOFTW
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Systematic Embedded Software Genera
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PART III: EMBEDDED SOFTWARE DESIGN
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Chapter 8 EXPLORING SW PERFORMANCE
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Exploring SW Performance 99 of late
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Exploring SW Performance 101 operat
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Exploring SW Performance 103 The ch
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Exploring SW Performance 105 2.2. T
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Exploring SW Performance 107 Figure
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Exploring SW Performance 109 modem
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Chapter 9 A FLEXIBLE OBJECT-ORIENTE
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A Flexible Object-Oriented Software
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Chapter 10 SCHEDULING AND TIMING AN
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Analysis of HW/SW On-Chip Communica
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Chapter 11 EVALUATION OF APPLYING S
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Evaluation of Applying SpecC to the
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Chapter 12 INTERACTIVE RAY TRACING
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Interactive Ray Tracing on Reconfig
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Chapter 13 PORTING A NETWORK CRYPTO
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Porting a Network Cryptographic Ser
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PART IV: EMBEDDED OPERATING SYSTEMS
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Chapter 14 INTRODUCTION TO HARDWARE
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Introduction to Hardware Abstractio
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Chapter 15 HARDWARE/SOFTWARE PARTIT
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Hardware and Software Partitioning
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Chapter 23 DYNAMIC PARALLELIZATION
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Dynamic Parallelization of Array 30
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Chapter 24 SDRAM-ENERGY-AWARE MEMOR
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SDRAM-Energy-Aware Memory Allocatio
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PART VII: SAFE AUTOMOTIVE SOFTWARE
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Chapter 25 SAFE AUTOMOTIVE SOFTWARE
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Safe Automotive Software Developmen
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PART VIII: EMBEDDED SYSTEM ARCHITEC
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Chapter 26 EXPLORING HIGH BANDWIDTH
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Exploring High Bandwidth Pipelined
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Chapter 27 ENHANCING SPEEDUP IN NET
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Enhancing Speedup in Network Proces
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Chapter 28 ON-CHIP STOCHASTIC COMMU
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On-Chip Stochastic Communication 37
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Chapter 29 HARDWARE/SOFTWARE TECHNI
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HW/SW are Techniques for Improving
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Chapter 30 RAPID CONFIGURATION & IN
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Rapid Configuration & Instruction S
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PART IX: TRANSFORMATIONS FOR REAL-T
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Chapter 31 GENERALIZED DATA TRANSFO
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Generalized Data Transformations 42
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Chapter 32 SOFTWARE STREAMING VIA B
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Software Streaming Via Block Stream
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Chapter 33 ADAPTIVE CHECKPOINTING W
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Adaptive Checkpointing with Dynamic
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PART X: LO POWER SOFTWARE
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Chapter 34 SOFTWARE ARCHITECTURAL T
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Software Architectural Transformati
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Chapter 35 DYNAMIC FUNCTIONAL UNIT
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Dynamic Functional Unit Assignment
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Chapter 36 ENERGY-AWARE PARAMETER P
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Energy-Aware Parameter Passing 501
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Chapter 37 LOW ENERGY ASSOCIATIVE D
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Low Energy Associative Data Caches
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INDEX abstract communication access
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Index 529 packet flows parameter pa
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