Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Enhancing Speedup in Network Processing Applications 363
Match (LPM) algorithm and is computed for every packet irrespective of
whether IR is exploited or not [6]. Most routers employ route caches to
minimize computing the LPM for every packet thereby ensuring that the
output port is known very early [6], Classification of flows based on the input
port involves little or no computation (since the input port through which a
packet arrives is known) but uncovers a smaller percentage of reuse for
some applications. In case of routers that have a large number of ports, a
many-to-one mapping between ports and RB’s to be queried by instructions
is necessary to obtain good results.
2.1. Proposed architecture
For single processor single threaded systems the architecture proposed in [1]
with a few minor changes is sufficient to exploit flow-based IR. However,
for multiprocessor and multithreaded systems, which are generally used in
designing NPUs, extra modifications are required. The essence of the problem
at hand is to determine the appropriate RB to be queried by instructions
operating on a packet and switch between RB’s when necessary. The NPU is
essentially a chip multiprocessor consisting of multiple RISC processors (or
micro-engines – using the terminology of Intel IXP1200 [7]) with support
for hardware multithreading. It is the job of the programmer to partition tasks
across threads as well as programs across micro-engines. The inter-thread and
inter-processor communication is explicitly managed by the user. Figure
27-2 shows the microarchitecture of a single processing engine. Each
processor has a RB array consisting of N + 1
is
the default RB that is queried by instructions before the flow id of a packet
is computed (for output port-based scheme only). The NPU also consists of
a Flow identifier table that is updated by the flow id for a given packet