Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Dynamic Parallelization of Array 317
whereas the remaining nests do not. Since the third nest of this application is
the one with the largest execution time‚ it dominates the overall energy-delay
product‚ leading to some gain when the entire application is considered. Hyper‚
on the other hand‚ benefits from the history based training. The last two bars
Figure 23-5 show‚ for each nest‚ the normalized energy-delay product due to
our strategy without and with past history information. Recall from Section
1.3.0 that when the history information is used‚ we can eliminate the training
overheads in successive visits. The results shown in the figure clearly indicate
that all nests in this application take advantage of history information‚ resulting
in a 9% improvement in the energy-delay product as compared to our strategy
without history information.
5. CONCLUDING REMARKS
On-chip multiprocessing is an attempt to speedup applications by exploiting
inherent parallelism in them. In this study‚ we have made three major contributions.
First‚ we have presented a runtime loop parallelization strategy
for on-chip multiprocessors. This strategy uses the initial iterations of a given
loop to determine the best number of processors to employ in executing the
remaining iterations. Second‚ we have quantified benefits of our strategy using
a simulation environment and showed how its behavior can be improved by
being more aggressive in determining the best number of processors. Third‚
we have demonstrated that the overheads associated with our approach can
be reduced using past history information about loop executions.